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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
SNGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
REJ03B0130-0100Z Rev.1.00 Apr 01, 2002
1. DESCRIPTION
The M37280MFH-XXXSP and M37280MKH-XXXSP are single-chip microcomputers designed with CMOS silicon gate technology. They have a OSD function and a data slicer function, so it is useful for a channel selection system for TV with a closed caption decoder. The feautures of the M37280EKSP is similar to those of the M37280MKH-XXXSP except that the chip has a built-in PROM which can be written electrically. The difference between M37280MKHXXXSP and M37280MFH-XXXSP are the ROM size and RAM size. Accordingly, the following descriptions will be for the M37280MKHXXXSP.
2. FEATURES
qNumber of basic instructions .................................................... 71 qMemory size ROM ................... 60K bytes (M37280MFH-XXXSP) 80K bytes (M37280MKH-XXXSP, -M37280EKSP) RAM .................. 1088 bytes (M37280MFH-XXXSP) 1536 bytes (M37280MKH-XXXSP, M37280EKSP) (*ROM correction memory included) qMinimum instruction execution time ......................................... 0.5 s (at 8 MHz oscillation frequency) qPower source voltage ................................................. 5 V 10 % qSubroutine nesting ............................................. 128 levels (Max.) qInterrupts ....................................................... 19 types, 16 vectors q8-bit timers .................................................................................. 6 qProgrammable I/O ports (Ports P0, P1, P2, P30, P31) ............. 26 qInput ports (Ports P40-P46, P63, P64, P70-P72) ...................... 12 qOutput ports (Ports P32, P47, P5, P60-P62, P65-P67) .............. 16 qLED drive ports ........................................................................... 2 qSerial I/O ............................................................ 8-bit 1 channel qMulti-master I2C-BUS interface .............................. 1 (2 systems) qA-D converter (8-bit resolution) .................................... 8 channels qPWM output circuit ......................................................... 8-bit 8 qPower dissipation In high-speed mode ......................................................... 165 mW (at VCC = 5.5V, 8 MHz oscillation frequency, CRT on, and Data slicer on) In low-speed mode ......................................................... 0.33 mW (at VCC = 5.5V, 32 kHz oscillation frequency) qROM correction function qClosed caption data slicer .............................................. 2 vectors
qOSD function Display characters .... 32 characters 16 lines + RAM font (1 character) (CC/OSD mode)(CDOSD mode)(RAM font) Kinds of characters ......... 510 kinds + 62 kinds + 1 kind (Coloring unit) (a character) (a dot) (a dot) Triple layer function ....................................................................... 2 layers selected from CC/CDOSD/OSD mode + RAM font layer Character display area .............. CC/CDOSD mode: 16 26 dots OSD mode/RAM font: 16 20 dots Kinds of character sizes .................... CC mode/RAM font: 4 kinds OSD/CDOSD mode: 14 kinds Kinds of character colors .............................................................. 64 colors (4 adjustment levels for each R, G, B) Coloring unit ............ dot, character, character background, raster Blanking output OUT1, OUT2 Display position Horizontal: 256 levels Vertical :1024 levels (RAM font can be set independently) Attribute ........................................................................................ CC mode: smooth italic, underline, flash, automatic solid space OSD mode: border, shadow Window/Blank function
3. APPLICATION
TV with a closed caption decoder
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TABLE OF CONTENTS
1. DESCRIPTION .......................................................................... 1 2. FEATURES ................................................................................ 1 3. APPLICATION ............................................................................ 1 4. PIN CONFIGURATION .............................................................. 3 5. FUNCTIONAL BLOCK DIAGRAM ............................................. 4 6. PERFORMANCE OVERVIEW ................................................... 5 7. PIN DESCRIPTION ................................................................... 7 8. FUNCTIONAL DESCRIPTION ................................................. 12 8.1. CENTRAL PROCESSING UNIT (CPU) ............................ 12 8.2 MEMORY .......................................................................... 13 8.3 INTERRUPTS .................................................................... 21 8.4 TIMERS ............................................................................. 26 8.5 SERIAL I/O ........................................................................ 30 8.6 MULTI-MASTER I2C-BUS INTERFACE ........................... 33 8.7 PWM OUTPUT CIRCUIT .................................................. 46 8.8 A-D CONVERTER ............................................................. 50 8.9 ROM CORRECTION FUNCTION ..................................... 54 8.10 DATA SLICER .................................................................. 55 8.11 OSD FUNCTIONS ........................................................... 66 8.11.1 Triple Layer OSD ................................................... 71 8.11.2 Display Position ..................................................... 74 8.11.3 Dot Size ................................................................. 78 8.11.4 Clock for OSD ....................................................... 79 8.11.5 Field Determination Display .................................. 81 8.11.6 Memory for OSD ................................................... 83 8.11.7 Character Color ..................................................... 91 8.11.8 Character Background Color ................................. 91 8.11.9 OUT1, OUT2 Signals ............................................ 95 8.11.10 Attribute ............................................................... 96 8.11.11 Multiline Display ................................................ 101 8.11.12 Automatic Solid Space Function ....................... 102 8.11.13 Scan Mode ........................................................ 103 8.11.14 Window Function ............................................... 104 8.11.15 Blank Function ................................................. 109 8.11.16 SPRITE OSD Function ...................................... 110 8.11.17 OSD Output Pin Control .................................... 114 8.11.18 Raster Coloring Function .................................. 115 8.12 SOFTWARE RUNAWAY DETECT FUNCTION ............. 117 8.13 RESET CIRCUIT ........................................................... 118 8.14 CLOCK GENERATING CIRCUIT .................................. 119 8.15 DISPLAY OSCILLATION CIRCUIT ................................ 122 8.16 AUTO-CLEAR CIRCUIT ................................................ 122 8.17 ADDRESSING MODE ................................................... 122 8.18 MACHINE INSTRUCTIONS .......................................... 122 9. PROGRAMMING NOTES ...................................................... 122 10. ABSOLUTE MAXIMUM RATINGS ....................................... 123 11. RECOMMENDED OPERATING CONDITIONS ................... 123 12. ELECTRIC CHARACTERISTICS ........................................ 124 13. ANALOG R, G, B OUTPUT CHARACTERISTICS ............... 126 14. A-D CONVERTER CHARACTERISTICS ............................. 126 15. MULTI-MASTER I2C-BUS BUS LINE CHARACTERISTICS ......... 127 16. PROM PROGRAMMING METHOD ..................................... 128 17. DATA REQUIRED FOR MASK ORDERS ............................ 129 18. APPENDIX ........................................................................... 130 19. PACKAGE OUTLINE ........................................................... 169
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4. PIN CONFIGURATION
HSYNC VSYNC P40AD4 P41/INT2 P42/TIM2 P43/TIM3 P24/AD3 P25/AD2 P26/AD1 P27/AD5 P00/PWM4 P50/PWM7 P01/PWM5 P47 P02/PWM6 P51 P17/SIN/R0 P32 P44/INT1 P56 P45/SOUT P57 P46/SCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P52/R/R1 P53/G/G1 P54/B/B1 P55/OUT1 P04/PWM0 P05/PWM1 P60 P06/PWM2 P61 P07/PWM3 P62 P20 P21 P22 P23 P10/OUT2 P65 P11/SCL1 P66 P12/SCL2 P67 P13/SDA1 P14/SDA2 P15/G0 P16/INT3/B0 P03/PWM7 P30/AD7 P31/AD8 RESET P64/OSC2/XCOUT P63/OSC1/XCIN VCC
M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
( )...M37280EKSP (AVCC
) NC HLF/AD6 P72/(SIN)
P71/VHOLD P70/CVIN CNVSS XIN XOUT VSS
Outline 64P4B
Note: Only 24th pin is NC pin of M37280MFH/ MKH-XXXSP. This pin is AVcc pin of M37280EKSP. But NC pin of M37280MFH/MKH-XXXSP is not connect in the IC. You can apply to Vcc.
Fig. 4.1 Pin Configuration (Top View)
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Input ports P70 - P72
(
) ... M37280EKSP Pins for data slicer VHOLD HLF CVIN RVCO
26 28 27 25 34 35
Clock input Clock output VSS CNVSS
32 29 36 24 33
XIN XOUT
Reset input (AVCC) RESET NC VCC
Input ports P63, P64 Clock input for Clock output for OSD/ OSD/sub-clock input sub-clock output OSC1 OSC2
SIN SCLK SOUT
SDA2 SDA1 SCL2 SCL1
PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0
P3 (3) P2 (8) P0 (8)
P1 (8)
P4 (8)
INT1 INT2
I2C-BUS interface
INT3
VSYNC
18 37 36
17 40 41 42 43 45 47 49
10 9 8 7 50 51 52 53 55 57 59 60 39 15 13 11
14 23 21 19 6 5 4 3
44 46 48 54 56 58 16 12 61 62 63 64 20 22 2
OUT1 B G R
Output port I/O ports P30, P31 P32 I/O port P2
I/O port P1
I/O port P0
Output port P47
Input ports P40-P46
Output ports Output port P5 P60-P62 , P65-P47
Sync signal input
HSYNC
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SI/O P7 (3) Data slicer A-D converter TIM2 TIM3
Program counter
30
31
Clock generating circuit Timer count source selection circuit
Fig. 5.1 Functional Block Diagram of M37280
Progam counter
5. FUNCTIONAL BLOCK DIAGRAM
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ROM Timer 1 T1 (8) Timer 2 T2 (8) Timer 3 T3 (8) PCH (8) PCL (8) Timer 4 T4 (8) Control signal
Index register Index register
Data bus
RAM
Address bus
8-bit arithmetic and logical unit X (8) Y (8) Stack pointer S (8) Timer 5 T5 (8) Timer 6 T6 (8) Instruction decoder Instruction register (8)
Accumulator A (8)
Processor status register PS (8)
OSD circuit
Multi-master
A-D converter SI/O (8)
8-bit PWM circuit P6 (8) P5 (8)
1
M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
6. PERFORMANCE OVERVIEW
Table 6.1 Performance Overview Parameter Number of basic instructions Instruction execution time Clock frequency Memory size Functions 71 0.5 s (the minimum instruction execution time, at 8 MHz oscillation frequency) 8 MHz (maximum) 60K bytes 80K bytes 1088 bytes (ROM correction memory inclued) 1536bytes (ROM correction memory inclued) 20400 bytes 9672 bytes 120 bytes 1536 bytes 7-bit 1 (N-channel open-drain output structure, can be used as 8-bit PWM output pins) 1-bit 1 (CMOS input/output structure, can be used as 14-bit PWM output pin) 4-bit 1 (CMOS input/output structure, can be used as OSD output pin, INT input pin, serial input pin) 4-bit 1 (N-channel open-drain output structure, can be used as multimaster I2C-BUS interface) 8-bit 1 (CMOS input/output structure, can be used as A-D input pins) 2-bit 1 (CMOS input/output structure, can be used as A-D input pins) 1-bit 1 (N-channel open-drain output structure) 5-bit 1 (can be used as A-D input pins, INT input pins, external clock input pins) 2-bit 1 (N-channel open-drain output structure when serial I/O is used, can be used as serial I/O pins) 1-bit 1 (N-channel open-drain output structure) 4-bit 1 (N-channel open-drain output structure, can be used as PWM output pin) 4-bit 1 (CMOS output structure, can be used as OSD output pins) 6-bit 1 (N-channel open-drain output structure) 1-bit 1 (can be used as sub-clock input pin, OSD clock input pin) 1-bit 1 (CMOS output structure when LC is oscillating, can be used as sub-clock output pin, OSD clock output pin) 3-bit 1 (can be used as data slicer input/output, serial input pin) 8-bit 1 1 (2 systems) 8 channels (8-bit resolution) 8-bit 8 8-bit timer 6 128 levels (maximum) <19 types> External interrupt 3, Internal timer interrupt 6, Serial I/O interrupt 1, OSD interrupt 1, Multi-master I 2 C-BUS interface interrupt 1, Data slicer interrupt 1, f(XIN)/4096 interrupt 1, SPRITE OSD interrupt 1, VSYNC interrupt 1, A-D conversion interrupt 1, BRK instruction interrupt 1 2 built-in circuits (externally connected to a ceramic resonator or a quartzcrystal oscillator) Built in
Input/Output ports
ROM M37280MFH-XXXSP M37280MKH-XXXSP, M37280EKSP RAM M37280MFH-XXXSP M37280MKH-XXXSP, M37280EKSP OSD ROM (character font) OSD ROM (color dot font) OSD RAM (SPRITE) OSD RAM (character) P00-P02, P04-P07 I/O P03 P10, P15-P17 P11-P14 P2 P30, P31 P32 P40-P44 P45, P46 P47 P50, P51, P56, P57 P52-P55 P60-P62, P65-P67 P63 P64 I/O I/O I/O I/O I/O Output Input Input Output Output Output Output Input Input Input
P70-P72 Serial I/O Multi-master I2C-BUS interface A-D converter PWM output circuit Timers Subroutine nesting Interrupt
Clock generating circuit Data slicer
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Table 6.2 Performance Overview Parameter Number of display characters Character display area Functions 32 characters 16 lines CC mode: 16 26 dots (dot structure: 16 20 dots) OSD mode: 16 20 dots EXOSD mode: 16 26 dots SPRITE display: 16 20 dots CC/OSD mode: 510 kinds CDOSD mode: 62 kinds SPRITE display: 1 kind CC mode: 2 kinds OSD/CDOSD mode: 14 kinds SPRITE display: 8 kinds CC/CDOSD mode: 8 kinds (R, G, B, OUT1, OUT2)) OSD mode: 15 kinds (R, G, B, OUT1, OUT2) SPRITE display: 8 kinds (R, G, B, OUT1) 256 levels (horizontal) 1024 levels (vertical) SPRITE display: 2048 1024 5V 10% 275 mW typ. ( at oscillation frequency f(XIN) = 8 MHz, fOSC = 27 MHz) 165 mW typ. ( at oscillation frequency f(XIN) = 8 MHz, fOSC = 27 MHz ) 82.5 mW typ. ( at oscillation frequency f(XIN) = 8 MHz) 0.33 mW typ. ( at oscillation frequency f(XCIN) = 32 kHz, f(XIN) = stop) 0.055 mW ( maximum ) -10 C to 70 C CMOS silicon gate process 64-pin shrink plastic molded DIP
OSD function
Kinds of characters
Kinds of character sizes
Kinds of character colors
Display position (horizontal, vertical) Power source voltage Power In high-speed dissipation mode OSD ON (Analog output) OSD ON (Digital output) OSD OFF OSD OFF Data slicer ON Data slicer OFF Data slicer OFF Data slicer OFF
In low-speed mode In stop mode Operating temperature range Device structure Package
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7. PIN DESCRIPTION
Table 7.1 Pin Description Pin VCC, (AVCC,) VSS CNVSS RESET Name Power source Input/ Output Functions Apply voltage of 5 V 10 % (typical) to VCC (AVCC ) , and 0 V to VSS. ( ) ...M37280EKSP Input Input Connected to VSS. To enter the reset state, the reset input pin must be kept at a LOW for 2 s or more (under normal VCC conditions). If more time is needed for the quartz-crystal oscillator to stabilize, this LOW condition should be maintained for the required time. This chip has an internal clock generating circuit. To control generating frequency, an external ceramic resonator or a quartz-crystal oscillator is connected between pins XIN and XOUT. If an external clock is used, the clock source should be connected to the XIN pin and the XOUT pin should be left open. Port P0 is an 8-bit I/O port with direction register allowing each I/O bit to be individually programmed as input or output. At reset, this port is set to input mode. The output structure of P03 is CMOS output, that of P00-P02 and P04-P07 are N-channel open-drain output. See notes at end of Table for full details of port P0 functions. Pins P00-P03 and P04-P07 are also used as 8-bit PWM output pins PWM4-PWM7 and PWM0-PWM3 respectively. The output structure of PWM0-PWM6 is N-channel open-drain output. And the output structure of PWM7 is CMOS output. Port P1 is an 8-bit I/O port and has basically the same functions as port P0. The output structure of P10 and P15-P17 is CMOS output, that of P11-P14 is N-channel open-drain output. Pin P10, P15-P17 are also used as OSD output pins OUT2, G0, B0, R0, respectively. The output structure is CMOS output. Pin P11-P14 are used as SCL1, SCL2, SDA1 and SDA2 respectively, when multi-master I2C-BUS interface is used. The output structure is N-channel open-drain output. Pin P16 is also used as extemal interrupt input pin INT3. Pin P17 is also used as serial I/O data input pin SIN. Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The output structure is CMOS output. Pins P24-P26, P27 are also used as analog input pins AD3-AD1, AD5 respectively. Ports P30 and P31 are 2-bit I/O ports and have basically the same functions as port P0. The output structure is CMOS output. Pins P30, P31 are also used as analog input pins AD7, AD8 respectively. Ports P32 is a 1-bit output port. The output structure is N-channel open-drain output. Ports P40-P46 are a 7-bit input port. Pin P40 is also used as analog input pin AD4. Pins P41, P44 are also used as external interrupt input pins INT2, INT1. Pins P42 and P43 are also used as external clock input pins TIM2, TIM3 respectively. Pin P45 is used as serial I/O data output pin SOUT. The output structure is N-channel opendrain output. Pin P46 is used as serial I/O synchronous clock input/output pin SCLK. The output structure is N-channel open-drain output. Port P47 is a 1-bit output port. The output structure is N-channel open-drain output.
CNVSS Reset input
XIN XOUT
Clock input Clock output
Input Output I/O
P00/ I/O port P0 PWM4- P02/PWM6, P03/PWM7, P04/ 8-bit PWM output PWM0- P07/PWM3 P10/OUT2, P11/SCL1, P12/SCL2, P13/SDA1, P14/SDA2, P15/G0, P16/INT3/ B0, P17/SIN/R0 I/O port P1
Output
I/O
OSD output Multi-master I2C-BUS interface External interrupt input Serial I/O data input I/O port P2 Analog input I/O port P3 Analog input Output port P3 Input port P4 Analog input External interrupt input External clock input Serial I/O data output Serial I/O synchronous clock input/output Output port P4
Output Output Input Input I/O Input I/O Input Output Input Input Input Input Output I/O
P20-P23 P24/AD3- P26/AD1, P27/AD5 P30/AD7, P31/AD8 P32 P40/AD4, P41/INT2, P42/TIM2, P43/TIM3, P44/INT1, P45/SOUT, P46/SCLK
P47
Output
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Table 7.2 Pin Description (continued) Pin P50/PWM7, P51, P52/R/R1, P53/G/G1, P54/B/B1, P55/OUT1, P56, P57 P60-P62, P65-P67 P63/OSC1/ XCIN, P64/OSC2/ XCOUT Name Output port P5 PWM output OSD output Input/ Output Output Output Output Functions Port P5 is a 4-bit output port. The output structure of P50, P51, P56 and P57 is N-channel open-drain output, that of P52-P55 is CMOS output. Pin P50 is also used as 8-bit PWM output pin PWM7. The output structure is N-channel open-drain output. Pins P52-P55 are also used as OSD output pins R/R1, G/G1, B/B1, OUT1 respectively. At R, G, B output, the output structure is analog output. At R1, G1, B1 and OUT1 output, the output structure is CMOS output. Ports P60-P62 and P65-P67 are 6-bit output ports. The output structure is N-channel opendrain output. Ports P63 and P64 are 2-bit input port. Pin P63 is also used as OSD clock input pin OSC1. Pin P64 is also used as OSD clock output pin OSC2. The output structure is CMOS output. Pin P64 is also used as sub-clock output pin XCOUT. The output structure is CMOS output. Pin P63 is also used as sub-clock input pin XCIN. Ports P70-P72 are 3-bit input port. Pins P70, P71 are also used as data slicer input pins CVIN, VHOLD respectively. When using data slicer, input composite video signal through a capacitor. Connect a capacitor between VHOLD and VSS. Pins P72 is also used as serial I/O data input pin SIN. When using data slicer, connect a filter using of a capacitor and a resistor between HLF and VSS. This is an analog input pin AD6 . This is a horizontal synchronous signal input for OSD. This is a vertical synchronous signal input for OSD.
Output port P6 Input port P6 Clock input for OSD Clock output for OSD Sub-clock output Sub-clock input Input port P7 Input for data slicer Serial I/O data input
Output Input Input Output Output Input Input Input
P70/CVIN, P71/VHOLD, P72/(SIN)
Input
HLF/AD6 Analog input HSYNC input VSYNC input Input Input Input
HSYNC VSYNC
Note : Port Pi (i = 0 to 3) has the port Pi direction which can be used to program each bit as an input ("0") or an output ("1"). The pins programmed as "1" in the direction register are output pins. When pins are programmed as "0," they are input pins. When pins are programmed as output pins, the output data are written into the port latch and then output. When data is read from the output pins, the output pin level is not read but the data of the port latch is read. This allows a previously-output value to be read correctly even if the output "L" voltage has risen, for example, because a light emitting diode was directly driven. The input pins float, so the values of the pins can be read. When data is written into the input pin, it is written only into the port latch, while the pin remains in the floating state.
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Ports P03, P10, P15-P17, P2, P30, P31
Direction register
CMOS output Ports P03, P10, P15-P17, P2, P30, P31 Note : Each port is also used as follows : P00 : PWM7 P10 : OUT2 P15 : G0 P16 : INT3/B0 P17 : SIN/R0 P24-P26 : AD3-AD1 P27 : AD5 P30 : AD7 P31 : AD8
Data bus
Port latch
Ports P00-P02, P04-P07 Direction register
N-channel open-drain output Ports P00-P02, P04-P07
Data bus
Port latch
Note 1 : Each port is also used as follows : P00-P02 : PWM4-PWM6 P04-P07 : PWM0-PWM3 2 : M37280EKSP does not have the diode side with VCC.
Ports P11-P14 Direction register
N-channel open-drain output Port P11-P14
Data bus
Port latch
Note : Each port is also used as follows : P11 : SCL1 P12 : SCL2 P13 : SDA1 P14 : SDA2
Fig. 7.1 I/O Pin Block Diagram (1)
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SOUT, SCLK
N-channel open-drain output
Direction register
Ports P45, P46
Data bus
Note : Each pin is also used as follows : P45 : SOUT P46 : SCLK
HSYNC, VSYNC
Port P55
Schmidt input HSYNC, VSYNC
Internal circuit
CMOS output
Port P55
Internal circuit
Note : Port P55 is also used as pin OUT1.
Ports P40-P44
Input Ports P40-P44
Data bus
Note : Each port is also used as below : P40 : AD4 P41 : INT2 P42 : TIM2 P43 : TIM3 P44 : INT1
Ports P32, P47, P51, P56, P57, P6 0-P62, P65-P67
N-chanel open drain output Ports P32, P47, P51, P56, P57, P60-P62, P65-P67
Data bus
Ports latch
N-chanel open drain output
Port P50
Port P50 Note 1: Port P50 is also used as pin PWM7. 2: M37280EKSP does not have the diode side with VCC.
Data bus
Ports latch
Fig. 7.2 I/O Pin Block Diagram (2)
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Ports P52-P54
Internal circuit
Output Ports P52-P54 Note : Each port is also used as below : P52 : R/R1 P53 : G/G1 P54 : B/B1
Fig. 7.3 I/O Pin Block Diagram (3)
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8. FUNCTIONAL DESCRIPTION 8.1. CENTRAL PROCESSING UNIT (CPU)
This microcomputer uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the SERIES 740 User's Manual for details on the instruction set. Machine-resident 740 Family instructions are as follows: The FST, SLW instruction cannot be used. The MUL, DIV, WIT and STP instructions can be used.
8.1.1 CPU Mode Register
The CPU mode register contains the stack page selection bit and internal system clock selection bit. The CPU mode register is allocated at address 00FB16.
CPU Mode Register
b7 b6 b5 b4 b3 b2 b1 b0 11 00 CPU mode register (CM) [Address 00FB16] Name Processor mode bits 0, 1 (CM0, CM1) B Functions
b1 b0
After reset R W 0 RW
0 0 1 1
0: Single-chip mode 1: 0: Not available 1: 1 1 RW RW RW RW
2 Stack page selection bit (CM2) (See note) 3, 4 Fix these bits to "1." 5 XCOUT drivability selection bit (CM5) 6 Main Clock (XIN-XOUT) stop bit (CM6) 7 Internal system clock selection bit (CM7)
0: 0 page 1: 1 page
0: LOW drive 1: HIGH drive 0: Oscillating 1: Stopped
1 0
0: XIN-XOUT selected (high-speed mode) 1: XCIN-XCOUT selected (low-speed mode) Note: This bit is set to "1" after the reset release.
0
RW
Fig. 8.1.1 CPU Mode Register
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8.2 MEMORY 8.2.1 Special Function Register (SFR) Area
The special function register (SFR) area in the zero page contains control registers such as I/O ports and timers.
8.2.6 Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
8.2.7 Zero Page
The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode.
8.2.2 RAM
RAM is used for data storage and for stack area of subroutine calls and interrupts.
8.2.3 ROM
The M37280MFH-XXXSP has 60K-byte program area. The M37280MKH -XXXSP has 56K-byte program area and 24K-byte datadedicated area. For the M37280EKSP, the two area (60K, 24K + 56K) can be swithed each other by setting the bank control register.
8.2.8 Special Page
The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode.
8.2.4 OSD RAM
RAM for display is used for specifying the character codes and colors to display.
8.2.9 ROM Correction Vector 8.2.5 OSD ROM
ROM for display is used for storing character data. This is used as the program jump destination addresses for ROM correction.
000016 00BF16 00C016 00FF16 010016 020016 025816 02C016 02FF16 030016 053F16
OSD RAM (SPRITE) (120 bytes) (See note 1) OSD RAM (character) (1536 bytes) (See note 2) Zero page
1000016 1080016
Not used
RAM (1472 bytes) for M37280MKH-XXXSP and M37280EKSP
RAM (1024 bytes) for M37280MFHXXXSP
SFR1 area
OSD ROM
SFR2 area Not used
(character font) (20400 bytes)
ROM correction function Vector 1 : address 02C016 Vector 2 : address 02E016 Not used
157FF16 Not used 1800016
06FF16 070016 07A716 080016
Not used
OSD ROM (color dot font) (9672 bytes)
0FFF16 100016
1ACFF16
Not used
1B00016
ROM (60K bytes) Expansion ROM (20K bytes) for M37280MKH-XXXSP
Bank 11 Bank 12 Bank 13 Bank 14
1C00016 1D00016 1E00016 1F00016
FF0016 FFDE16 FFFF16
and M37280EKSP
Interrupt vector area
Special page
Bank 15 1FFFF16 Notes 1: Refer to Table 8.11.4 OSD RAM (SPRITE). 2: Refer to Tables 8.11.5 and 8.11.6 OSD RAM (character).
Fig. 8.2.1 Memory Map
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
8.2.10 Expansion ROM (only M37280MKHXXXSP/M37280EKSP)
The M37280MKH-XXXSP/M37280EKSP can use 5-bank (total 20K bytes) expansion ROM (4K bytes each bank) by setting the bank register. The expansion ROM is assigned to address 1B00016 to 1FFFF16. The contents of each bank in the expansion ROM are read by setting the bank register and accessing addresses 100016 to 1FFF16. As the expansion ROM is not programmable, use it as data-dedicated area. When using the expansion ROM area, the internal ROM at addresses 100016 to 1FFF16 (extra area) is not also programmable.
Notes 1: When using the expansion ROM (BK7 = "1"), the ROM correction function do not operate for addresses 100016 to 1FFF16. 2: When using the emulator MCU (M37280ERSS), as addresses 100016 to FFFF16 can be emulated by setting bit 7 of the bank control register to "0," the expansion ROM cannot be used. Addresses 200016 to FFFF16 can be emulated by setting it to "1." The data in specified area by the bank selection bits can be read by accessing addresses 100016 to 1FFF16. 3: When using the emulator MCU, the expansion ROM and the extra area cannot be emulated by setting bit 7 of the bank control register to "1." Therefore, write the data to this area before using. 4: For the M37280MKH-XXXSP, fix bit 7 of the bank control register to "1." For M37280MFH-XXXSP, fix the address 00ED16 to "0016."
Bank Control Register
b7 b6 b5 b4 b3 b2 b1 b0
00
Bank control register (BK) [Address 00ED16]
B 0 to 3
Name
Functions
After reset R W 0 RW
Bank Bank number is selected (bank 11 to 15) selection bits (BK0 to BK3)
4, 5 Fix these bits to "0". 6, 7 Bank control bits (BK6, BK7) b7 b6 Bank ROM Address 100016 level access 0 Not used Read out from extra area (programmable) 1 0 Used Read out the data from area specified by the bank selection bits Read out from extra area 1 1 Used (data-dedicated)
0 0
RW RW
Fig. 8.2.2 Bank Control Register
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
s SFR1 area (addresses C016 to DF16)

:
Name
:
Function bit
0 : "0" immediately after reset 1 : "1" immediately after reset ? : Indeterminate immediately after reset
: No function bit 0 : Fix to this bit to "0" (do not write to "1") 1 : Fix to this bit to "1" (do not write to "0") Bit allocation
b7
Address C016 C116 C216 C316 C416 C516 C616 C716 C816 C916 CA16 CB16 CC16 CD16 CE16 CF16 D016 D116 D216 D316 D416 D516 D616 D716 D816 D916 DA16 DB16 DC16 DD16 DE16 DF16
Register
State immediately after reset
b0 b7 b0
Port P0 (P0) Port P0 direction register (D0) Port P1 (P1) Port P1 direction register (D1) Port P2 (P2) Port P2 direction register (D2) Port P3 (P3) Port P3 direction register (D3) Port P4 (P4) Port P4 direction register (D4) Port P5 (P5) OSD port control register (PF) Port P6 (P6) Port P7 (P7) OSD control register 1 (OC 1) Horizontal position register (HP) Block control register 1 (BC 1) Block control register 2 (BC 2) Block control register 3 (BC 3) Block control register 4 (BC 4) Block control register 5 (BC 5) Block control register 6 (BC 6) Block control register 7 (BC 7) Block control register 8 (BC 8) Block control register 9 (BC 9) Block control register 10 (BC10) Block control register 11 (BC11) Block control register 12 (BC12) Block control register 13 (BC13) Block control register 14 (BC14) Block control register 15 (BC15) Block control register 16 (BC16)
P6IM T3CS
0 0
OUT2 OUT1
B
G
R
RGB 2BIT
0 0 0 0
OC17 OC16 OC15 OC14 OC13 OC12 OC11 OC10 HP17 HP16 HP15 HP14 HP13 HP12 HP11 HP10 BC16 BC15 BC14 BC13 BC12 BC11 BC10 BC26 BC25 BC24 BC23 BC22 BC21 BC20 BC36 BC35 BC34 BC33 BC32 BC31 BC30 BC46 BC45 BC44 BC43 BC42 BC41 BC40 BC56 BC55 BC54 BC53 BC52 BC51 BC50 BC66 BC65 BC64 BC63 BC62 BC61 BC60 BC76 BC75 BC74 BC73 BC72 BC71 BC70 BC86 BC85 BC84 BC83 BC82 BC81 BC80 BC96 BC95 BC94 BC93 BC92 BC91 BC90
BC106 BC105 BC104 BC103 BC102 BC101 BC100 BC116 BC115 BC114 BC113 BC112 BC111 BC110 BC126 BC125 BC124 BC123 BC122 BC121 BC120 BC136 BC135 BC134 BC133 BC132 BC131 BC130 BC146 BC145 BC144 BC143 BC142 BC141 BC140 BC156 BC155 BC154 BC153 BC152 BC151 BC150 BC166 BC165 BC164 BC163 BC162 BC161 BC160
? 0016 ? 0016 ? 0016 ? 0016 ? 0016 ? 0016 ? 00 0016 0016 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
?
?
?
Fig. 8.2.3 Memory Map of Special Function Register 1 (SFR1) (1)
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
s SFR1 area (addresses E016 to FF16)

:
Name
Function bit
0 : "0" immediately after reset 1 : "1" immediately after reset ? : Indeterminate immediately after reset
: : No function bit
0 : Fix to this bit to "0" (do not write to "1") 1 : Fix to this bit to "1" (do not write to "0") Address E016 E116 E216 E316 E416 E516 E616 E716 E816 E916 EA16 EB16 EC16 ED16 EE16 EF16 F016 F116 F216 F316 F416 F516 F616 F716 F816 F916 FA16 FB16 FC16 FD16 FE16 FF16 Register
b7 Data slicer control register 1 (DSC1) Data slicer control register 2 (DSC2) Caption data register 1 (CD1) Caption data register 2 (CD2) Caption data register 3 (CD3) Caption data register 4 (CD4) Caption Position register (CPS) Data slicer test register 2 Data slicer test register 1
Sync signal counter register (HC) Clock run-in detect register (CRD) Data clock position register (DPS)
Bit allocation 0 0 0 0 0 0
DSC12 DSC11 DSC10
State immediately after reset
b0 b7 b0
DSC25 DSC24 DSC23
0
DSC20
?
0
?
CDL17 CDL16 CDL15 CDL14 CDL13 CDL12 CDL11 CDL10 CDH17 CDH16 CDH15 CDH14 CDH13 CDH12 CDH11 CDH10 CDL27 CDL26 CDL25 CDL24 CDL23 CDL22 CDL21 CDL20 CDH27 CDH26 CDH25 CDH24 CDH23 CDH22 CDH21 CDH20 CPS7 CPS6 CPS5 CPS4 CPS3 CPS2 CPS1 CPS0
0
0
?
0016 0016
HC5 HC4 HC3 HC2 HC1 HC0
CRD7 CRD6 CRD5 CRD4 CRD3 DPS7 DPS6 DPS5 DPS4 DPS3
0
0
?
0
0
1
BK7 BK6 0 Bank control register (BK) 0 BK3 BK2 BK1 BK0 A-D conversion register (AD) A-D control register (ADCON) 0 0 ADVREF ADSTR ADIN2 ADIN1 ADIN0 Timer 1 (T1) Timer 2 (T2) Timer 3 (T3) Timer 4 (T4) Timer mode register 1 (TM1) TM17 TM16 TM15 TM14 TM13 TM12 TM11 TM10 Timer mode register 2 (TM2) TM27 TM26 TM25 TM24 TM23 TM22 TM21 TM20 D7 D6 D5 D4 D3 D2 D1 D0 I2C data shift register (S0) SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW 2C address register (S0D) I MST TRX BB PIN AL AAS AD0 LRB I2C status register (S1) 10BIT BSEL BSEL 2C control register (S1D) I SAD ALS ESO BC2 BC1 BC0 2 C clock control register (S2) ACK ACK FAST CCR4 CCR3 CCR2 CCR1 CCR0 I BIT MODE CM7 CM6 CM5 1 CPU mode register (CM) 1 CM2 0 0 Interrupt request register 1 (IREQ1) ADR VSCR OSDR TM4R TM3R TM2R TM1R Interrupt request register 2 (IREQ2) 0 TM56R IICR IN2R CKR SIOR DSR IN1R CK0 Interrupt control register 1 (ICON1) ADE VSCE OSDE TM4E TM3E TM2E TM1E Interrupt control register 2 (ICON2) TM56S TM56E IICE IN2E CKE SIOE DSE IN1E
0
?
0
0
0
0
0016 0? 0016 0016 0016 0016 00 0016 0016 ?? 0016 0916 ? 0016 ? 01 FF16 0716 FF16 0716 0016 0016 ? 0016 10 0016 0016 3C16 0016 0016 0016 0016
?
0
?
0
0
0
?
?
?
0
0
0
0
0
?
Fig. 8.2.4 Memory Map of Special Function Register 1 (SFR2) (2)
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
s SFR2 area (addresses 20016 to 21F16)

:
Name
Function bit
0 : "0" immediately after reset 1 : "1" immediately after reset ? : Indeterminate immediately after reset
: : No function bit
0 : Fix to this bit to "0" (do not write to "1") 1 : Fix to this bit to "1" (do not write to "0") Address 20016 20116 20216 20316 20416 20516 20616 20716 20816 20916 20A16 20B16 20C16 20D16 20E16 20F16 21016 21116 21216 21316 21416 21516 21616 21716 21816 21916 21A16 21B16 21C16 21D16 21E16 21F16 Register
b7 PWM0 register (PWM0) PWM1 register (PWM1) PWM2 register (PWM2) PWM3 register (PWM3) PWM4 register (PWM4) PWM5 register (PWM5) PWM6 register (PWM6) PWM7 register (PWM7)
Bit allocation
b0 b7
State immediately after reset
b0
PWM mode register 1 (PN) PN4 PN3 PN0 PWM mode register 2 (PW) PW7 PW6 PW5 PW4 PW3 PW2 PW1 PW0 ROM correction address 1 (high-order) ROM correction address 1 (low-order) ROM correction address 2 (high-order) ROM correction address 2 (low-order) ROM correction enable register (RCR) Test register Interrupt input polarity register (IP) Serial I/O mode register (SM) Serial I/O register (SIO) OSD control register 2(OC2) Clock control register (CS) I/O polarity control register (PC) Raster color register (RC) OSD control register 3(OC3) Timer 5 (TM5) Timer 6 (TM6) Top border control register 1 (TB1) Bottom border control register 1 (BB1) Top border control register 1 (TB2) Bottom border control register 1 (BB2)
TB17 TB16 TB15 TB14 TB13 TB12 TB11 TB10 BB17 BB16 BB15 BB14 BB13 BB12 BB11 BB10 TB21 TB20 BB21 BB20 OC27 OC26 OC25 OC24 OC23 OC12 OC21 OC20
AD/INT3 SEL AD/INT3 PC7 SEL AD/INT3 SEL AD/INT3 INT3 SEL POL AD/INT3 SEL AD/INT3 SEL
RE5
RE3 0 00 16
RE2 RCR1 RCR0 0 RE1
INT3 POL3 RE5 POL2 POL1 RE2 RE3 POL INT3 SM6 RE5 SM4 RE3 RE2 SM3 SM2 POL SM5
RE1 SM1 RE1 SM0
INT3 0 POL INT3 PC6 POL INT3 POL
0
0
0
RE2 CS2
RE1 CS0 CS1 PC1 RE1 PC0 RC1 RE1 RC0
PC5 RE5 PC4
RE3 RE2 PC2
RE5 RC4 RC3 RE2 RE3 RC2
OC37 OC36 OC35 OC34 OC33 RE2 RE1 OC30 RE3 OC32 OC31
? ? ? ? ? ? ? ? ? ? 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 ? 0016 0016 8016 0016 0016 0716 FF16 ? ? ? ?
Fig. 8.2.5 Memory Map of Special Function Register 2 (SFR2) (1)
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
s SFR2 area (addresses 22016 to 23F16)
:
Name
0 : "0" immediately after reset 1 : "1" immediately after reset ? : Indeterminate immediately after reset
:
Function bit
: No function bit 0 : Fix to this bit to "0" (do not write to "1") 1 : Fix to this bit to "1" (do not write to "0") Bit allocation
b7
1 2 3
Address 22016 22116 22216 22316 22416 22516 22616 22716 22816 22916 22A16 22B16 22C16 22D16 22E16 22F16 23016 23116 23216 23316 23416 23516 23616 23716 23816 23916 23A16 23B16 23C16 23D16 23E16 23F16
Register
(VP1 1 ) (VP1 2 )
b0 b7
State immediately after reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
b0
Vertical position register 1 Vertical position register 1 Vertical position register 1 Vertical position register 1 Vertical position register 1 Vertical position register 1 Vertical position register 1 Vertical position register 1 Vertical position register 1 Vertical position register 1 Vertical position register 1 Vertical position register 1 Vertical position register 1 Vertical position register 1 Vertical position register 1 Vertical position register 1 Vertical position register 2 Vertical position register 2 Vertical position register 2 Vertical position register 2 Vertical position register 2 Vertical position register 2 Vertical position register 2 Vertical position register 2 Vertical position register 2 Vertical position register 2 Vertical position register 2 Vertical position register 2 Vertical position register 2 Vertical position register 2 Vertical position register 2 Vertical position register 2
VP117 VP116 VP115 VP114 VP113 VP112 VP111 VP110 VP127 VP126 VP125 VP124 VP123 VP122 VP121 VP120 VP137 VP136 VP135 VP134 VP133 VP132 VP131 VP130 VP147 VP146 VP145 VP144 VP143 VP142 VP141 VP140 VP157 VP156 VP155 VP154 VP153 VP152 VP151 VP150 VP167 VP166 VP165 VP164 VP163 VP162 VP161 VP160 VP177 VP176 VP175 VP174 VP173 VP172 VP171 VP170 VP187 VP186 VP185 VP184 VP183 VP182 VP181 VP180 VP197 VP196 VP195 VP194 VP193 VP192 VP191 VP190
(VP1 3 ) 4 (VP1 4 ) 5 (VP1 5 ) 6 (VP1 6 ) (VP1 7 ) 8 (VP1 8 ) 9 (VP1 9 )
7
) 10 (VP1 10 ) VP1107 VP1106 VP1105 VP1104 VP1103 VP1102 VP1101 VP1100 ) 11 (VP1 11 ) VP1117 VP1116 VP1115 VP1114 VP1113 VP1112 VP1111 VP1110 ) 12 (VP1 12 ) VP1127 VP1126 VP1125 VP1124 VP1123 VP1122 VP1121 VP1120 (VP1 13 ) 14 (VP1 14 ) 15 (VP1 15 ) 16 (VP1 16 ) 1 (VP2 1 )
13 2 (VP2 2 ) 3 (VP2 3 )
VP1137 VP1136 VP1135 VP1134 VP1133 VP1132 VP1131 VP1130 ) VP1147 VP1146 VP1145 VP1144 VP1143 VP1142 VP1141 VP1140 ) VP1157 VP1156 VP1155 VP1154 VP1153 VP1152 VP1151 VP1150 ) VP1167 VP1166 VP1165 VP1164 VP1163 VP1162 VP1161 VP1160 ) VP211 VP210 VP221 VP220 VP231 VP230 VP241 VP240 VP251 VP250 VP261 VP260 VP271 VP270 VP281 VP280 VP291 VP290 VP2101 VP2100 VP2111 VP2110 VP2121 VP2120 VP2131 VP2130 VP2141 VP2140 VP2151 VP2150 VP2161 VP2160
(VP2 4 ) 5 (VP2 5 ) 6 (VP2 6 )
4
(VP2 7 ) 8 (VP2 8 ) 9 (VP2 9 )
7 10 (VP2 10 ) 11 (VP2 11 ) 12 (VP2 12 )
(VP2 13 ) 14 (VP2 14 ) 15 (VP2 15 ) 16 (VP2 16 )
13
Fig. 8.2.6 Memory Map of Special Function Register 2 (SFR2) (2)
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
s SFR2 area (addresses 24016 to 25816)

:
Name
Function bit
0 : "0" immediately after reset 1 : "1" immediately after reset ? : Indeterminate immediately after reset
: : No function bit
0 : Fix to this bit to "0" (do not write to "1") 1 : Fix to this bit to "1" (do not write to "0") Address 24016 24116 24216 24316 24416 24516 24616 24716 24816 24916 24A16 24B16 24C16 24D16 24E16 24F16 25016 25116 25216 25316 25416 Register
b7 Color pallet register 1 (CR1) Color pallet register 2 (CR2) Color pallet register 3 (CR3) Color pallet register 4 (CR4) Color pallet register 5 (CR5) Color pallet register 6 (CR6) Color pallet register 7 (CR7) Color pallet register 9 (CR9) Color pallet register10 (CR10) Color pallet register 11 (CR11) Color pallet register 12 (CR12) Color pallet register 13 (CR13) Color pallet register 14 (CR14) Color pallet register 15 (CR15) Left border control register 1 (LB1) Left border control register 2 (LB2) Right border control register 1 (RB1) Right border control register 2 (RB2)
SPRITE vertical position register 1 (VS1)
Bit allocation
State immediately after reset
b0 b7 b0
CR16 CR15 CR14 CR13 CR12 CR11 CR10 CR26 CR25 CR24 CR23 CR22 CR21 CR20 CR36 CR35 CR34 CR33 CR32 CR31 CR30 CR46 CR45 CR44 CR43 CR42 CR41 CR40 CR56 CR55 CR54 CR53 CR52 CR51 CR50 CR66 CR65 CR64 CR63 CR62 CR61 CR60 CR76 CR75 CR74 CR73 CR72 CR71 CR70 CR96 CR95 CR94 CR93 CR92 CR91 CR90
CR106 CR105 CR104 CR103 CR102 CR101 CR100 CR116 CR115 CR114 CR113 CR112 CR111 CR110 CR126 CR125 CR124 CR123 CR122 CR121 CR120 CR136 CR135 CR134 CR133 CR132 CR131 CR130 CR146 CR145 CR144 CR143 CR142 CR141 CR140 CR156 CR155 CR154 CR153 CR152 CR151 CR150 LB17 LB16 LB15 LB14 LB13 LB12 LB11 LB10 LB22 LB21 LB20 RB17 RB16 RB15 RB14 RB13 RB12 RB11 RB10 RB22 RB21 RB20 VS17 VS16 VS15 VS14 VS13 VS12 VS11 VS10 VS21 VS20 HS17 HS16 HS15 HS14 HS13 HS12 HS11 HS10 HS22 HS21 HS20 SC5 SC4 SC3 SC2 SC1 SC0
25516 SPRITE vertical position register 2 (VS2) 25616 SPRITE horizontal position register 1 (HS1) 25716 SPRITE horizontal position register 2 (HS2) 25816 SPRITE OSD control register (SC)
0
0
0
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0116 0016 FF16 0716 ? 0016 ? 00 0016
?
?
?
Fig. 8.2.7 Memory Map of Special Function Register 2 (SFR2) (3)
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
:
Name
0 : "0" immediately after reset 1 : "1" immediately after reset ? : Indeterminate immediately after reset
Function bit
: : No function bit
0 : Fix to this bit to "0" (do not write to "1") 1 : Fix to this bit to "1" (do not write to "0") Register
b7 Processor status register (PS) Program counter (PCH) Program counter (PCL)
Bit allocation
b0 b7
State immediately after reset
b0
N
V
T
B
D
I
Z
C
?????1?? Contents of address FFFF16 Contents of address FFFE16
Fig. 8.2.8 Internal State of Processor Status Register and Program Counter at Reset
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
8.3 INTERRUPTS
Interrupts can be caused by 19 different sources consisting of 3 external, 14 internal, 1 software, and reset. Interrupts are vectored interrupts with priorities as shown in Table 8.3.1. Reset is also included in the table because its operation is similar to an interrupt. When an interrupt is accepted, x The contents of the program counter and processor status regis ter are automatically stored into the stack. The interrupt disable flag I is set to "1" and the corresponding interrupt request bit is set to "0." The jump destination address stored in the vector address enters the program counter. Other interrupts are disabled when the interrupt disable flag is set to "1." All interrupts except the BRK instruction interrupt have an interrupt request bit and an interrupt enable bit. The interrupt request bits are in interrupt request registers 1 and 2 and the interrupt enable bits are in interrupt control registers 1 and 2. Figures 8.3.2 to 8.3.6 show the interrupt-related registers. Interrupts other than the BRK instruction interrupt and reset are accepted when the interrupt enable bit is "1," interrupt request bit is "1," and the interrupt disable flag is "0." The interrupt request bit can be set to "0" by a program, but not set to "1." The interrupt enable bit can be set to "0" and "1" by a program. Reset is treated as a non-maskable interrupt with the highest priority. Figure 8.3.1 shows interrupt control.
8.3.1 Interrupt Causes
(1) VSYNC and OSD Interrupts The VSYNC interrupt is an interrupt request synchronized with the vertical sync signal. The OSD interrupt occurs after character block display to the CRT is completed. (2) INT1, INT2 Interrupts The INT1 and INT2 interrupts are external interrupt inputs, the system detects that the level of a pin changes from LOW to HIGH or from HIGH to LOW, and generates an interrupt request. The input active edge can be selected by bits 3 and 4 of the interrupt input polarity register (address 021216) : when this bit is "0," a change from LOW to HIGH is detected; when it is "1," a change from HIGH to LOW is detected. Note that both bits are cleared to "0" at reset. (3) Timer 1 to 4 Interrupts An interrupt is generated by an overflow of timer 1, 2, 3 or 4.
Table 8.3.1 Interrupt Vector Addresses and Priority Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Interrupt Source Reset OSD interrupt INT1 interrupt Data slicer interrupt Serial I/O interrupt Timer 4 * SPRITE OSD interrupt f(XIN)/4096 interrupt VSYNC interrupt Timer 3 interrupt Timer 2 interrupt Timer 1 interrupt A-D convertion * INT3 interrupt INT2 interrupt Multi-master I2C-BUS interface interrupt Timer 5 * 6 interrupt BRK instruction interrupt Vector Addresses FFFF16, FFFE16 FFFD16, FFFC16 FFFB16, FFFA16 FFF916, FFF816 FFF716, FFF616 FFF516, FFF416 FFF316, FFF216 FFF116, FFF016 FFEF16, FFEE16 FFED16, FFEC16 FFEB16, FFEA16 FFE916, FFE816 FFE716, FFE616 FFE516, FFE416 FFE316, FFE216 FFDF16, FFDE16 Remarks Non-maskable Active edge selectable
Software switch by software (See note) Active edge selectable
Software switch by software (See note)/ When selecting INT3 interrupt, active edge selectable. Active edge selectable Software switch by software (See note) Non-maskable (software interrupt)
Note : Switching a source during a program causes an unnecessary interrupt occurs. Accordingly, set a source at initializing of program.
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
(4) Serial I/O Interrupt This is an interrupt request from the clock synchronous serial I/O function. (5) f(XIN)/4096 * SPRITE OSD Interrupt The f (XIN)/4096 interrupt occurs regularly with a f(XIN)/4096 period. Set bit 0 of the PWM mode register 1 to "0." The SPRITE OSD interrupt occurs at the completion of SPRITE display. Since f(XIN)/4096 interrupt and SPRITE OSD interrupt share the same vector, an interrupt source is selected by bit 5 of the SPRITE OSD control register (address 025816). (6) Data Slicer Interrupt An interrupt occurs when slicing data is completed. (7) Multi-master I2C-BUS Interface Interrupt This is an interrupt request related to the multi-master I2C-BUS interface. (8) A-D Conversion * INT3 Interrupt The A-D conversion interrupt occurs at the completion of A-D conversion. The INT3 is an external input,the system detects that the level of a pin changes from LOW to HIGH or from HIGH to LOW, and generates an interrupt request. The input active edge can be selected by bit 6 of the interrupt input polarity register (address 021216) : when this bit is "0," a change from LOW to HIGH is detected; when it is "1," a change from HIGH to LOW is detected. Note that this bit is cleared to "0" at reset. Since A-D conversion interrupt and the INT3 interrupt share the same vector, an interrupt source is selected by bit 7 of the interrupt interval determination control register (address 021216). (9) Timer 5 * 6 Interrupt An interrupt is generated by an overflow of timer 5 or 6. Their priorities are same, and can be switched by software. (10) BRK Instruction Interrupt This software interrupt has the least significant priority. It does not have a corresponding interrupt enable bit, and it is not affected by the interrupt disable flag I (non-maskable). Fig. 8.3.1 Interrupt Control
Interrupt request bit Interrupt enable bit
Interrupt disable flag I
BRK instruction Reset
Interrupt request
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
Interrupt Request Register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) [Address 00FC16] B 0 1 2 3 4 5 6 7 After reset Name Functions 0 : No interrupt request issued Timer 1 interrupt 0 request bit (TM1R) 1 : Interrupt request issued Timer 2 interrupt 0 : No interrupt request issued 0 request bit (TM2R) 1 : Interrupt request issued Timer 3 interrupt 0 : No interrupt request issued 0 request bit (TM3R) 1 : Interrupt request issued Timer 4 interrupt 0 0 : No interrupt request issued request bit (TM4R) 1 : Interrupt request issued OSD interrupt request 0 : No interrupt request issued 0 bit (OSDR) 1 : Interrupt request issued VSYNC interrupt 0 0 : No interrupt request issued request bit (VSCR) 1 : Interrupt request issued A-D conversion * INT3 0 : No interrupt request issued 0 interrupt request bit (ADR) 1 : Interrupt request issued Nothing is assigned. This bit is a write disable bit. 0 When this bit is read out, the value is "0." RW R R R R R R R R--
: "0" can be set by software, but "1" cannot be set.
Fig. 8.3.2 Interrupt Request Register 1
Interrupt Request Register 2
b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt request register 2 (IREQ2) [Address 00FD16] B Functions After reset 0 : No interrupt request issued 0 1 : Interrupt request issued 0 : No interrupt request issued 0 1 : Interrupt request issued 0 : No interrupt request issued 0 1 : Interrupt request issued 0 : No interrupt request issued 0 1 : Interrupt request issued 0 : No interrupt request issued 0 1 : Interrupt request issued 0 : No interrupt request issued 0 5 Multi-master I2C-BUS interrupt request bit (IICR) 1 : Interrupt request issued 6 Timer 5 * 6 interrupt 0 : No interrupt request issued 0 request bit (TM56R) 1 : Interrupt request issued 7 Fix this bit to "0." 0 : "0" can be set by software, but "1" cannot be set. Name INT1 interrupt 0 request bit (IN1R) 1 Data slicer interrupt request bit (DSR) 2 Serial I/O interrupt request bit (SIOR) 3 f(XIN)/4096 * SPRITE OSD interrupt request bit (CKR) 4 INT2 interrupt request bit (IN2R) RW R R R R R R R RW
Fig. 8.3.3 Interrupt Request Register 2
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
Interrupt Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address 00FE16] B 0 Functions After reset 0 0 : Interrupt disabled 1 : Interrupt enabled 0 1 Timer 2 interrupt 0 : Interrupt disabled enable bit (TM2E) 1 : Interrupt enabled 0 2 Timer 3 interrupt 0 : Interrupt disabled enable bit (TM3E) 1 : Interrupt enabled 0 3 Timer 4 interrupt 0 : Interrupt disabled enable bit (TM4E) 1 : Interrupt enabled 0 4 OSD interrupt enable bit 0 : Interrupt disabled (OSDE) 1 : Interrupt enabled 5 VSYNC interrupt enable 0 : Interrupt disabled 0 bit (VSCE) 1 : Interrupt enabled 6 A-D conversion * INT3 0 0 : Interrupt disabled interrupt enable bit (ADE) 1 : Interrupt enabled 0 7 Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0." Name Timer 1 interrupt enable bit (TM1E) RW RW RW RW RW RW RW RW R--
Fig. 8.3.4 Interrupt Control Register 1
Interrupt Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 2 (ICON2) [Address 00FF16] B 0 1 2 3 4 5 6 7 Name INT1 interrupt enable bit (IN1E) Data slicer interrupt enable bit (DSE) Serial I/O interrupt enable bit (SIOE) f(XIN/4096 * SPRITE OSD interrupt enable bit (CKE) INT2 interrupt enable bit (IN2E) Multi-master I2C-BUS interface interrupt enable bit (IICE) Timer 5 * 6 interrupt enable bit (TM56E) Timer 5 * 6 interrupt switch bit (TM56S) After reset Functions 0 0: Interrupt disabled 1: Interrupt enabled 0 0: Interrupt disabled 1: Interrupt enabled 0 0: Interrupt disabled 1: Interrupt enabled 0 0: Interrupt disabled 1: Interrupt enabled 0: Interrupt disabled 0 1: Interrupt enabled 0 0: Interrupt disabled 1: Interrupt enabled 0 0: Interrupt disabled 1: Interrupt enabled 0 0: Timer 5 1: Timer 6 RW RW RW RW RW RW RW RW RW
Fig. 8.3.5 Interrupt Control Register 2
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Interrupt Input Polarity Register
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt input polarity register (IP) [Address 021216]
B
Name
Functions
After reset 0 0 0
RW R-- RW RW
0 to 2 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0." 3 4 INT1 polarity switch bit (POL1) INT2 polarity switch bit (POL2) 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity
5 6 7
Nothing is assigned. This bit is write disable bit. When this bit is read out, the value is "0." INT3 polarity switch bit (POL3) A-D conversion * INT3 interrupt source selection bit (AD/INT3SEL) 0 : Positive polarity 1 : Negative polarity 0 : INT3 interrupt 1 : A-D conversion interrupt
0 0 0
R-- RW RW
Fig. 8.3.6 Interrupt Input Polarity Register
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8.4 TIMERS
This microcomputer has 6 timers: timer 1, timer 2, timer 3, timer 4, timer 5, and timer 6. All timers are 8-bit timers with the 8-bit timer latch. The timer block diagram is shown in Figure 8.4.3. All of the timers count down and their divide ratio is 1/(n+1), where n is the value of timer latch. By writing a count value to the corresponding timer latch (addresses 00F016 to 00F316 : timers 1 to 4, addresses 021A16 and 021B16 : timers 5 and 6), the value is also set to a timer, simultaneously. The count value is decremented by 1. The timer interrupt request bit is set to "1" by a timer overflow at the next count pulse, after the count value reaches "0016".
8.4.5 Timer 5
Timer 5 can select one of the following count sources: * f(XIN)/16 or f(XCIN)/16 * Timer 2 overflow signal * Timer 4 overflow signal The count source of timer 3 is selected by setting bit 6 of timer mode register 1 (address 00F416) and bit 7 of timer mode register 2 (address 00F516). When overflow of timer 2 or 4 is a count source for timer 5, either timer 2 or 4 functions as an 8-bit prescaler. Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. Timer 5 interrupt request occurs at timer 5 overflow.
8.4.6 Timer 6 8.4.1 Timer 1
Timer 1 can select one of the following count sources: * f(XIN)/16 or f(XCIN)/16 * f(XIN)/4096 or f(XCIN)/4096 * External clock from the P42/TIM2 pin The count source of timer 1 is selected by setting bits 5 and 0 of timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. Timer 1 interrupt request occurs at timer 1 overflow. Timer 6 can select one of the following count sources: * f(XIN)/16 or f(XCIN)/16 * Timer 5 overflow signal The count source of timer 6 is selected by setting bit 7 of timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. When timer 5 overflow signal is a count source for timer 6, timer 5 functions as an 8-bit prescaler. Timer 6 interrupt request occurs at timer 6 overflow. At reset, timers 3 and 4 are connected by hardware and "FF16" is automatically set in timer 3; "0716" in timer 4. The f(XIN) /16 is selected as the timer 3 count source. The internal reset is released by timer 4 overflow in this state and the internal clock is connected. At execution of the STP instruction, timers 3 and 4 are connected by hardware and "FF16" is automatically set in timer 3; "0716" in timer 4. However, the f(XIN) /16 is not selected as the timer 3 count source. So set both bit 0 of timer mode register 2 (address 00F516) and bit 6 at address 00C716 to "0" before execution of the STP instruction (f(XIN) /16 is selected as the timer 3 count source). The internal STP state is released by timer 4 overflow in this state and the internal clock is connected. As a result of the above procedure, the program can start under a stable clock. : When bit 7 of the CPU mode register (CM7) is "1," f(XIN) becomes f(XCIN). The structure of timer-related registers is shown in Figures 8.4.1 and 8.4.2.
8.4.2 Timer 2
Timer 2 can select one of the following count sources: * f(XIN)/16 or f(XCIN)/16 * Timer 1 overflow signal * External clock from the TIM2 pin The count source of timer 2 is selected by setting bits 4 and 1 of timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. When timer 1 overflow signal is a count source for the timer 2, the timer 1 functions as an 8bit prescaler. Timer 2 interrupt request occurs at timer 2 overflow.
8.4.3 Timer 3
Timer 3 can select one of the following count sources: * f(XIN)/16 or f(XCIN)/16 * f(XCIN) * External clock from the TIM3 pin The count source of timer 3 is selected by setting bit 0 of timer mode register 2 (address 00F516) and bit 6 at address 00C716. Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. Timer 3 interrupt request occurs at timer 3 overflow.
8.4.4 Timer 4
Timer 4 can select one of the following count sources: * f(XIN)/16 or f(XCIN)/16 * f(XIN)/2 or f(XCIN)/2 * f(XCIN) The count source of timer 3 is selected by setting bits 1 and 4 of timer mode register 2 (address 00F516). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. When timer 3 overflow signal is a count source for the timer 4, the timer 3 functions as an 8bit prescaler. Timer 4 interrupt request occurs at timer 4 overflow.
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Timer Mode Register 1
b7 b6 b5 b4 b3 b2 b1 b0 Timer mode register 1 (TM1) [Address 00F416] B 0 1 Name Timer 1 count source selection bit 1 (TM10) Timer 2 count source selection bit 1 (TM11) After reset R W Functions 0: f(XIN)/16 or f(XCIN)/16 (Note) 0 RW 1: Count source selected by bit 5 of TM1 0: Count source selected by bit 4 of TM1 1: External clock from TIM2 pin 0: Count start 1: Count stop 0: Count start 1: Count stop 0 0 0 0 0 0 0 RW RW RW RW RW RW RW
2 Timer 1 count stop bit (TM12) 3 Timer 2 count stop bit (TM13)
4 Timer 2 count source 0: f(XIN)/16 or f(XCIN)/16 (See note) selection bit 2 (TM14) 1: Timer 1 overflow 5 Timer 1 count source selection bit 2 (TM15) 6 Timer 5 count source selection bit 2 (TM16) 7 Timer 6 internal count source selection bit (TM17) 0: f(XIN)/4096 or f(XCIN)/4096 (See note) 1: External clock from TIM2 pin 0: Timer 2 overflow 1: Timer 4 overflow 0: f(XIN)/16 or f(XCIN)/16 (See note) 1: Timer 5 overflow
Note: Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register.
Fig. 8.4.1 Timer Mode Register 1
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Timer Mode Register 2
b7 b6 b5 b4 b3 b2 b1 b0 Timer mode register 2 (TM2) [Address 00F516] B Name 0 Timer 3 count source selection bit (TM20) Functions (b6 at address 00C716) 0 1 0 1 1, 4 Timer 4 count source selection bits (TM21, TM24) b4 0 0 1 1 b0 0 : f(XIN)/16 or f(XCIN)/16 (See note) 0 : f(XCIN) 1: 1 : External clock from TIM3 pin b1 0 : Timer 3 overflow signal 1 : f(XIN)/16 or f(XCIN)/16 (See note) 0 : f(XIN)/2 or f(XCIN)/2 (See note) 1 : f(XCIN) 0 RW After reset R W 0 RW
2 Timer 3 count stop bit (TM22) 3 Timer 4 count stop bit (TM23) 5 Timer 5 count stop bit (TM25) 6 Timer 6 count stop bit (TM26)
0: Count start 1: Count stop 0: Count start 1: Count stop 0: Count start 1: Count stop 0: Count start 1: Count stop
0 0 0 0
RW RW RW RW
7 Timer 5 count source 0: f(XIN)/16 or f(XCIN)/16 (See note) RW 0 1: Count source selected by bit 6 selection bit 1 of TM1 (TM27) Note: Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register.
Fig. 8.4.2 Timer Mode Register 2
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Data bus
8
XCIN
CM7 TM15 1/4096 Timer 1 latch (8)
8
XIN
1/2
1/8
TM10 TM12 TM14
Timer 1 (8)
8 8
Timer 1 interrupt request
Timer 2 latch (8)
8
TIM2 TM11 TM13
Timer 2 (8) 8
8
Timer 2 interrupt request
FF16 T3CS Timer 3 latch (8)
8
Reset STP instruction
TIM3 TM20 TM22
Timer 3 (8) 8
8
Timer 3 interrupt request
TM21
0716 Timer 4 latch (8)
8
Timer 4 (8) TM21 TM24 TM23 TM16 Selection gate : Connected to black side at reset TM1 : Timer mode register 1 TM2 : Timer mode register 2 T3CS : Timer 3 count source switch bit (address 00C716) CM : CPU mode register TM27 TM25 8
8
Timer 4 interrupt request 8
8
Timer 5 latch (8)
8
Timer 5 (8)
Timer 5 interrupt request
Timer 6 latch (8)
8
Timer 6 (8) TM17 TM26 8
Timer 6 interrupt request
Notes 1: HIGH pulse width of external clock inputs TIM2 and TIM3 needs 4 machine cycles or more. 2: When the external clock source is selected, timers 1, 2, and 3 are counted at a rising edge of input signal. 3: In the stop mode or the wait mode, external clock inputs TIM2 and TIM3 cannot be used.
Fig. 8.4.3 Timer Block Diagram
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8.5 SERIAL I/O
This microcomputer has a built-in serial I/O which can either transmit or receive 8-bit data serially in the clock synchronous mode. The serial I/O block diagram is shown in Figure 8.5.1. The synchronous clock I/O pin (SCLK), and data output pin (SOUT) also function as port P4, data input pin (SIN) also functions as ports P1 and P7. Bit 2 of the serial I/O mode register (address 021316) selects whether the synchronous clock is supplied internally or externally (from the SCLK pin). When an internal clock is selected, bits 1 and 0 select whether f(XIN) or f(XCIN) is divided by 8, 16, 32, or 64. To use SOUT and SCLK pins for serial I/O, set the corresponding bits of the port P4 direction register (address 00C916) to "0." To use SIN pin for serial I/O, set the corresponding bit of the port P1 direction register (address 00C316) to "0."
The operation of the serial I/O is described below. The operation of the serial I/O differs depending on the clock source; external clock or internal clock.
XCIN 1/2 XIN 1/2 CM7
Synchronous circuit
Data bus 1/2 Frequency divider
1/2 1/4 1/8 1/16
SM2
SM1 SM0
Selection gate: Connect to black side at reset.
SCLK
Serial I/O counter (8)
CM : CPU mode register SM : Serial I/O mode register Serial I/O interrupt request
SOUT SIN
SM5 : LSB
MSB (Note)
Serial I/O shift register (8) 8 (Address 021416)
Note : When the data is set in the serial I/O register (address 021416), the register functions as the serial I/O shift register.
Fig. 8.5.1 Serial I/O Block Diagram
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Internal clock : The serial I/O counter is set to "7" during the write cycle into the serial I/O register (address 021416), and the transfer clock goes "H" forcibly. At each falling edge of the transfer clock after the write cycle, serial data is output from the SOUT pin. Transfer direction can be selected by bit 5 of the serial I/O mode register. At each rising edge of the transfer clock, data is input from the SIN pin and data in the serial I/O register is shifted 1 bit. After the transfer clock has counted 8 times, the serial I/O counter becomes "0" and the transfer clock stops at HIGH. At this time the interrupt request bit is set to "1."
External clock : The an external clock is selected as the clock source, the interrupt request is set to "1" after the transfer clock has been counted 8 counts. However, transfer operation does not stop, so the clock should be controlled externally. Use the external clock of 500kHz or less with a duty cycle of 50%. The serial I/O timing is shown in Figure 8.5.2. When using an external clock for transfer, the external clock must be held at HIGH for initializing the serial I/O counter. When switching between an internal clock and an external clock, do not switch during transfer. Also, be sure to initialize the serial I/O counter after switching.
Notes 1: On programming, note that the serial I/O counter is set by writing to the serial I/O register with the bit managing instructions, such as SEB and CLB. 2: When an external clock is used as the synchronous clock, write transmit data to the serial I/O register when the transfer clock input level is HIGH.
Synchronous clock
Transfer clock Serial I/O register write signal (Note) Serial I/O output SOUT Serial I/O input SIN D0 D1 D2 D3 D4 D5 D6 D7
Interrupt request bit is set to "1" Note : When an internal clock is selected, the SOUT pin is at high-impedance after transfer is completed.
Fig. 8.5.2 Serial I/O Timing (for LSB first)
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Serial I/O Mode Register
b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O mode register (SM) [Address 021316] B Name b1 0 0 1 1 Functions b0 0: f(XIN)/8 or f(XCIN)/8 1: f(XIN)/16 or f(XCIN)/16 0: f(XIN)/32 or f(XCIN)/32 1: f(XIN)/64 or f(XCIN)/64 After reset R W 0 RW
0, 1 Internal synchronous clock selection bits (SM0, SM1)
2 3
Synchronous clock selection bit (SM2) Port function selection bit (SM3)
0: External clock 1: Internal clock 0: P11, P13 1: SCL1, SDA1 0: P12, P14 1: SCL2, SDA2 0: LSB first 1: MSB first 0: P17 is SIN pin. 1: P72 is SIN pin.
0 0
RW RW
4 Port function selection bit (SM4) 5 6 7 Transfer direction selection bit (SM5) SIN pin switch bit (SM6)
0 0 0 0
RW RW RW R--
Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0."
Fig. 8.5.3 Serial I/O Mode Register
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8.6 MULTI-MASTER I2C-BUS INTERFACE
The multi-master I2C-BUS interface is a serial communications circuit, conforming to the Philips I2C-BUS data transfer format. This interface, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial communications. Figure 8.6.1 shows a block diagram of the multi-master I2C-BUS interface and Table 8.6.1 shows multi-master I2C-BUS interface functions. This multi-master I2C-BUS interface consists of the I2C address register, the I2C data shift register, the I2C clock control register, the I2C control register, the I2C status register and other control circuits.
Table 8.6.1 Multi-master I2C-BUS Interface Functions Item Function In conformity with Philips I2C-BUS standard: 10-bit addressing format 7-bit addressing format High-speed clock mode Standard clock mode In conformity with Philips I2C-BUS standard: Master transmission Master reception Slave transmission Slave reception 16.1 kHz to 400 kHz (at = 4 MHz)
Format
Communication mode
SCL clock frequency
: System clock = f(XIN)/2
Note : We are not responsible for any third party's infringement of patent rights or other rights attributable to the use of the control function (bits 6 and 7 of the I2C control register at address 00F916) for connections between the I2C-BUS interface and ports (SCL1, SCL2, SDA1, SDA2).
b7
I2C address register (S0D) b0
Interrupt generating circuit Interrupt request signal (IICIRQ)
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
Address comparator Serial data
(SDA)
Noise elimination circuit
Data control circuit
b7
I C data shift register S0
2
b0 b7
MST TRX BB PIN
b0
AL AAS AD0 LRB
AL circuit
Internal data bus
I C status register (S1)
2
BB circuit
Serial clock
(SCL)
Noise elimination circuit
Clock control circuit
b7
ACK
b0
ACK FAST CCR4 CCR3 CCR2 CCR1 CCR0 MODE BIT
b7
BSEL1 BSEL0 10BIT SAD ALS
b0
ESO BC2 BC1 BC0
I2C clock control register (S2) Clock division
I2C control register (S1D) System clock () Bit counter
Fig. 8.6.1 Block Diagram of Multi-master I2C-BUS Interface
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8.6.1 I2C Data Shift Register
The I2C data shift register (S0 : address 00F616) is an 8-bit shift register to store receive data and write transmit data. When transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the SCL clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. When data is received, it is input to this register from bit 0 in synchronization with the SCL clock, and each time one-bit data is input, the data of this register are shifted one bit to the left. The I2C data shift register is in a write enable status only when the ESO bit of the I2C control register (address 00F916) is "1." The bit counter is reset by a write instruction to the I2C data shift register. When both the ESO bit and the MST bit of the I2C status register (address 00F816) are "1," the SCL is output by a write instruction to the I2C data shift register. Reading data from the I2C data shift register is always enabled regardless of the ESO bit value.
Note: To write data into the I2C data shift register after setting the MST bit to "0" (slave mode), keep an interval of 8 machine cycles or more.
I2C Data Shift Register
b7 b6 b5 b4 b3 b2 b1 b0 I2C data shift register 1 (S0) [Address 00F616]
B 0 to 7
Name D0 to D7
Functions This is an 8-bit shift register to store receive data and write transmit data.
2
After reset
RW
Indeterminate R W
Note: To write data into the I C data shift register after setting the MST bit to "0" (slave mode), keep an interval of 8 machine cycles or more.
Fig. 8.6.2 Data Shift Register
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8.6.2 I2C Address Register
The I2C address register (address 00F716) consists of a 7-bit slave address and a read/write bit. In the addressing mode, the slave address written in this register is compared with the address data to be received immediately after the START condition are detected. (1) Bit 0: Read/Write Bit (RBW) Not used when comparing addresses, in the 7-bit addressing mode. In the 10-bit addressing mode, the first address data to be received is compared with the contents (SAD6 to SAD0 + RBW) of the I2C address register. The RBW bit is cleared to "0" automatically when the stop condition is detected. (2) Bits 1 to 7: Slave Address (SAD0-SAD6) These bits store slave addresses. Regardless of the 7-bit addressing mode and the 10-bit addressing mode, the address data transmitted from the master is compared with the contents of these bits.
I2C Address Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C address register (S0D) [Address 00F716] B
0 1 to 7
Name
Read/write bit (RBW) Slave address (SAD0 to SAD6) 0: Read 1: Write
Functions
After reset R W
0 0
R-- RW
The address data transmitted from the master is compared with the contents of these bits.
Fig. 8.6.3 I2C Address Register
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8.6.3 I2C Clock Control Register
The I2C clock control register (address 00FA16) is used to set ACK control, SCL mode and SCL frequency. (1) Bits 0 to 4: SCL Frequency Control Bits (CCR0-CCR4) These bits control the SCL frequency. (2) Bit 5: SCL Mode Specification Bit (FAST MODE) This bit specifies the SCL mode. When this bit is set to "0," the standard clock mode is set. When the bit is set to "1," the high-speed clock mode is set. (3) Bit 6: ACK Bit (ACK BIT) This bit sets the SDA status when an ACK clock is generated. When this bit is set to "0," the ACK return mode is set and SDA goes to LOW at the occurrence of an ACK clock. When the bit is set to "1," the ACK non-return mode is set. The SDA is held in the HIGH status at the occurrence of an ACK clock. However, when the slave address matches the address data in the reception of address data at ACK BIT = "0," the SDA is automatically made LOW (ACK is returned). If there is a mismatch between the slave address and the address data, the SDA is automatically made HIGH (ACK is not returned). ACK clock: Clock for acknowledgement
(4) Bit 7: ACK Clock Bit (ACK) This bit specifies a mode of acknowledgment which is an acknowledgment response of data transmission. When this bit is set to "0," the no ACK clock mode is set. In this case, no ACK clock occurs after data transmission. When the bit is set to "1," the ACK clock mode is set and the master generates an ACK clock upon completion of each 1-byte data transmission.The device for transmitting address data and control data releases the SDA at the occurrence of an ACK clock (make SDA HIGH) and receives the ACK bit generated by the data receiving device.
Note: Do not write data into the I2C clock control register during transmission. If data is written during transmission, the I2C clock generator is reset, so that data cannot be transmitted normally.
I2C Clock Control Register
b7 b6 b5 b4 b3 b2 b1 b0 I2C clock control register (S2) [Address 00FA16]
B
0 to 4
Name
Functions
High speed clock mode
After reset R W
0
SCL frequency control bits Setup value of Standard clock CCR4-CCR0 mode (CCR0 to CCR4) 00 to 02 03 04 05 06 1D 1E 1F
RW
Setup disabled Setup disabled Setup disabled Setup disabled 100 83.3
500/CCR value
333 250 400 (See note) 166
1000/CCR value
...
17.2 16.6 16.1
34.5 33.3 32.3 0
(at = 4 MHz, unit : kHz) 5 SCL mode specification bit (FAST MODE) ACK bit (ACK BIT) ACK clock bit (ACK) 0: Standard clock mode 1: High-speed clock mode 0: ACK is returned. 1: ACK is not returned. 0: No ACK clock 1: ACK clock
RW RW RW
6 7
0 0
Note: At 400 kHz in the high-speed clock mode, the duty is as below . "0" period : "1" period = 3 : 2 In the other cases, the duty is as below. "0" period : "1" period = 1 : 1
Fig. 8.6.4 I2C Address Register
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8.6.4 I2C Control Register
The I2C control register (address 00F916) controls the data communication format. (1) Bits 0 to 2: Bit Counter (BC0-BC2) These bits decide the number of bits for the next 1-byte data to be transmitted. An interrupt request signal occurs immediately after the number of bits specified with these bits are transmitted. When a START condition is received, these bits become "0002" and the address data is always transmitted and received in 8 bits. (2) Bit 3: I2C Interface Use Enable Bit (ESO) This bit enables usage of the multimaster I2C BUS interface. When this bit is set to "0," the use disable status is provided, so the SDA and the SCL become high-impedance. When the bit is set to "1," use of the interface is enabled. When ESO = "0," the following is performed. * PIN = "1," BB = "0" and AL = "0" are set (they are bits of the I2C status register at address 00F816 ). * Writing data to the I2C data shift register (address 00F616) is disabled.
(3) Bit 4: Data Format Selection Bit (ALS) This bit decides whether or not to recognize slave addresses. When this bit is set to "0," the addressing format is selected, so that address data is recognized. When a match is found between a slave address and address data as a result of comparison or when a general call (refer to "8.6.5 I2C Status Register," bit 1) is received, transmission processing can be performed. When this bit is set to "1," the free data format is selected, so that slave addresses are not recognized. (4) Bit 5: Addressing Format Selection Bit (10BIT SAD) This bit selects a slave address specification format. When this bit is set to "0," the 7-bit addressing format is selected. In this case, only the high-order 7 bits (slave address) of the I2C address register (address 00F716) are compared with address data. When this bit is set to "1," the 10-bit addressing format is selected, all the bits of the I2C address register are compared with address data. (5) Bits 6 and 7:Connection Control Bits between I2C-BUS Interface and Ports (BSEL0, BSEL1) These bits controls the connection between SCL and ports or SDA and ports (refer to Figure 8.6.5).
"0" "1" BSEL0 SCL1/P11 SCL Multi-master I2C-BUS interface SDA "0" "1" BSEL1 SCL2/P12 "0" "1" BSEL0 SDA1/P13 "0" "1" BSEL1 SDA2/P14
Note: When using multi-master I2C-BUS interface, set bits 3 and 4 of the serial I/O mode register (address 021316) to "1." Moreover, set the corresponding direction register to "1" to use the port as multi-master I2C-BUS interface. Fig. 8.6.5 Connection Port Control by BSEL0 and BSEL1
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I2C Control Register
b7 b6 b5 b4 b3 b2 b1 b0 I2C control register (S1D) [Address 00F916]
B
0 to 2
Name
Bit counter (Number of transmit/recieve bits) (BC0 to BC2) b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1
Functions
b0 0: 8 1: 7 0: 6 1: 5 0: 4 1: 3 0: 2 1: 1
After reset R W
0
RW
3 4 5
I2C-BUS interface use enable bit (ESO) Data format selection bit(ALS) Addressing format selection bit (10BIT SAD)
0: Disabled 1: Enabled 0: Addressing format 1: Free data format 0: 7-bit addressing format 1: 10-bit addressing format b7 b6 Connection port (See note) 0 0: None 0 1: SCL1, SDA1 1 0: SCL2, SDA2 1 1: SCL1, SDA1, SCL2, SDA2
0 0 0 0
RW RW RW RW
6, 7 Connection control bits 2 between I C-BUS interface and ports (BSEL0, BSEL1)
Fig. 8.6.6 I2C Control Register
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8.6.5 I2C Status Register
The I2C status register (address 00F816) controls the I2C-BUS interface status. The low-order 4 bits are read-only bits and the highorder 4 bits can be read out and written to. (1) Bit 0: Last Receive Bit (LRB) This bit stores the last bit value of received data and can also be used for ACK receive confirmation. If ACK is returned when an ACK clock occurs, the LRB bit is set to "0." If ACK is not returned, this bit is set to "1." Except in the ACK mode, the last bit value of received data is input. The state of this bit is changed from "1" to "0" by executing a write instruction to the I2C data shift register (address 00F616). (2) Bit 1: General Call Detecting Flag (AD0) This bit is set to "1" when a general call whose address data is all "0" is received in the slave mode. By a general call of the master device, every slave device receives control data after the general call. The AD0 bit is set to "0" by detecting the STOP condition or START condition. General call: The master transmits the general call address "0016" to all slaves. (3) Bit 2: Slave Address Comparison Flag (AAS) This flag indicates a comparison result of address data. s In the slave receive mode, when the 7-bit addressing format is selected, this bit is set to "1" in one of the following conditions. * The address data immediately after occurrence of a START condition matches the slave address stored in the high-order 7 bits of the I2C address register (address 00F716). * A general call is received. s In the slave reception mode, when the 10-bit addressing format is selected, this bit is set to "1" with the following condition. * When the address data is compared with the I2C address register (8 bits consists of slave address and RBW), the first bytes match. s The state of this bit is changed from "1" to "0" by executing a write instruction to the I2C data shift register (address 00F616). (4) Bit 3: Arbitration Lost detecting flag (AL) n the master transmission mode, when a device other than the microcomputer sets the SDA to "L,", arbitration is judged to have been lost, so that this bit is set to "1." At the same time, the TRX bit is set to "0," so that immediately after transmission of the byte whose arbitration was lost is completed, the MST bit is set to "0." When arbitration is lost during slave address transmission, the TRX bit is set to "0" and the reception mode is set. Consequently, it becomes possible to receive and recognize its own slave address transmitted by another master device. Arbitration lost: The status in which communication as a master is disabled.
(5) Bit 4: I2C-BUS Interface Interrupt Request Bit (PIN) This bit generates an interrupt request signal. Each time 1-byte data is transmitted, the state of the PIN bit changes from "1" to "0." At the same time, an interrupt request signal is sent to the CPU. The PIN bit is set to "0" in synchronization with a falling edge of the last clock (including the ACK clock) of an internal clock and an interrupt request signal occurs in synchronization with a falling edge of the PIN bit. When the PIN bit is "0," the SCL is kept in the "0" state and clock generation is disabled. Figure 8.6.8 shows an interrupt request signal generating timing chart. The PIN bit is set to "1" in any one of the following conditions. * Executing a write instruction to the I2C data shift register (address 00F616). * When the ESO bit is "0" * At reset The conditions in which the PIN bit is set to "0" are shown below: * Immediately after completion of 1-byte data transmission (including when arbitration lost is detected) * Immediately after completion of 1-byte data reception * In the slave reception mode, with ALS = "0" and immediately after completion of slave address or general call address reception * In the slave reception mode, with ALS = "1" and immediately after completion of address data reception (6) Bit 5: Bus Busy Flag (BB) This bit indicates the status of use of the bus system. When this bit is set to "0," this bus system is not busy and a START condition can be generated. When this bit is set to "1," this bus system is busy and the occurrence of a START condition is disabled by the START condition duplication prevention function (Note). This flag can be written by software only in the master transmission mode. In the other modes, this bit is set to "1" by detecting a START condition and set to "0" by detecting a STOP condition. When the ESO bit of the I2C control register (address 00F916) is "0" and at reset, the BB flag is kept in the "0" state. (7) Bit 6: Communication Mode Specification Bit (transfer direction specification bit: TRX) This bit decides the direction of transfer for data communication. When this bit is "0," the reception mode is selected and the data of a transmitting device is received. When the bit is "1," the transmission mode is selected and address data and control data are output into the SDA in synchronization with the clock generated on the SCL. When the ALS bit of the I2C control register (address 00F916) is "0" in the slave reception mode is selected, the TRX bit is set to "1" (transmit) if the least significant bit (R/W bit) of the address data transmitted by the master is "1." When the ALS bit is "0" and the R/W bit is "0," the TRX bit is cleared to "0" (receive). The TRX bit is cleared to "0" in one of the following conditions. * When arbitration lost is detected. * When a STOP condition is detected. * When occurence of a START condition is disabled by the START condition duplication prevention function (Note). * With MST = "0" and when a START condition is detected. * With MST = "0" and when ACK non-return is detected. * At reset
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(8) Bit 7: Communication Mode Specification Bit (master/slave specification bit: MST) This bit is used for master/slave specification for data communication. When this bit is "0," the slave is specified, so that a START condition and a STOP condition generated by the master are received, and data communication is performed in synchronization with the clock generated by the master. When this bit is "1," the master is specified and a START condition and a STOP condition are generated, and also the clocks required for data communication are generated on the SCL. The MST bit is cleared to "0" in one of the following conditions. * Immediately after completion of 1-byte data transmission when arbitration lost is detected * When a STOP condition is detected. * When occurence of a START condition is disabled by the START condition duplication preventing function (Note). * At reset
Note: The START condition duplication prevention function disables the START condition generation, reset of bit counter reset, and SCL output, when the following condition is satisfied: a START condition is set by another master device.
I2C Status Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C status register (S1) [Address 00F816] B
0 1 2 3 4 5
Name
Last receive bit (LRB) (See note) General call detecting flag (AD0) (See note) Slave address comparison flag (AAS) (See note) Arbitration lost detecting flag (AL) (See note) I2C-BUS interface interrupt request bit (PIN) Bus busy flag (BB)
Functions
0 : Last bit = "0 " 1 : Last bit = "1 " (See note)
After reset R W
Indeterminate 0 0
R-- R-- R-- R-- RW RW RW
0 : No general call detected 1 : General call detected (See note) 0 : Address match 1 : Address mismatch 0 : Not detected 1 : Detected (See note)
0 0 0 0
(See note) 0 : Interrupt request issued 1 : No interrupt request issued 0 : Bus free 1 : Bus busy
6, 7 Communication mode specification bits (TRX, MST)
b7 0 0 1 1
b6 0 : Slave recieve mode 1 : Slave transmit mode 0 : Master recieve mode 1 : Master transmit mode
Note : These bits and flags can be read out, but cannnot be written.
Fig. 8.6.7 I2C Status Register
SCL PIN
IICIRQ
Fig. 8.6.8 Interrupt Request Signal Generation Timing
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8.6.6 START Condition Generation Method
When the ESO bit of the I2C control register (address 00F916) is "1," execute a write instruction to the I2C status register (address 00F816) to set the MST, TRX and BB bits to "1." A START condition will then be generated. After that, the bit counter becomes "0002" and an SCL for 1 byte is output. The START condition generation timing and BB bit set timing are different in the standard clock mode and the highspeed clock mode. Refer to Figure 8.6.9 for the START condition generation timing diagram, and Table 8.6.2 for the START condition/ STOP condition generation timing table.
I2C status register write signal SCL SDA BB flag Setup time Setup time Hold time Set time for BB flag
Fig. 8.6.9 START Condition Generation Timing Diagram
8.6.7 STOP Condition Generation Method
When the ESO bit of the I2C control register (address 00F916) is "1," execute a write instruction to the I2C status register (address 00F816) for setting the MST bit and the TRX bit to "1" and the BB bit to "0". A STOP condition will then be generated. The STOP condition generation timing and the BB flag reset timing are different in the standard clock mode and the high-speed clock mode. Refer to Figure 8.6.10 for the STOP condition generation timing diagram, and Table 8.6.2 for the START condition/STOP condition generation timing table.
I2C status register write signal SCL SDA BB flag Setup time Hold time Reset time for BB flag
Fig. 8.6.10 STOP Condition Generation Timing Diagram
Table 8.6.2 START Condition/STOP Condition Generation Timing Table Item Setup time Hold time Set/reset time for BB flag Standard Clock Mode 4.25 s (17 cycles) 5.0 s (20 cycles) 3.0 s (12 cycles) High-speed Clock Mode 1.75 s (7 cycles) 2.5 s (10 cycles) 1.5 s (6 cycles)
Note: Absolute time at = 4 MHz. The value in parentheses denotes the number of cycles.
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8.6.8 START/STOP Condition Detect Conditions
The START/STOP condition detect conditions are shown in Figure 8.6.11 and Table 8.6.3. Only when the 3 conditions of Table 8.6.3 are satisfied, a START/STOP condition can be detected.
Note: When a STOP condition is detected in the slave mode (MST = 0), an interrupt request signal "IICIRQ" is generated to the CPU.
8.6.9 Address Data Communication
There are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. The respective address communication formats is described below. (1) 7-bit Addressing Format To meet the 7-bit addressing format, set the 10BIT SAD bit of the I2C control register (address 00F916) to "0." The first 7-bit address data transmitted from the master is compared with the high-order 7-bit slave address stored in the I2C address register (address 00F716). At the time of this comparison, address comparison of the RBW bit of the I2C address register (address 00F716) is not made. For the data transmission format when the 7-bit addressing format is selected, refer to Figure 8.6.12, (1) and (2). (2) 10-bit Addressing Format To meet the 10-bit addressing format, set the 10BIT SAD bit of the I2C control register (address 00F916) to "1." An address comparison is made between the first-byte address data transmitted from the master and the 7-bit slave address stored in the I2C address register (address 00F716). At the time of this comparison, an address comparison between the RBW bit of the I2C address register (address 00F716) and the R/W bit which is the last bit of the address data transmitted from the master is made. In the 10-bit addressing mode, the R/W bit which is the last bit of the address data not only specifies the direction of communication for control data but also is processed as an address data bit. When the first-byte address data matches the slave address, the AAS bit of the I2C status register (address 00F816) is set to "1." After the second-byte address data is stored into the I2C data shift register (address 00F616), make an address comparison between the second-byte data and the slave address by software. When the address data of the 2nd bytes matches the slave address, set the RBW bit of the I2C address register (address 00F716) to "1" by software. This processing can match the 7-bit slave address and R/W data, which are received after a RESTART condition is detected, with the value of the I2C address register (address 00F716). For the data transmission format when the 10-bit addressing format is selected, refer to Figure 8.6.12, (3) and (4).
SCL release time SCL SDA (START condition) SDA (STOP condition) Setup time Setup time Hold time Hold time
Fig. 8.6.11 START Condition/STOP Condition Detect Timing Diagram
Table 8.6.3 START Condition/STOP Condition Detect Conditions Standard Clock Mode 6.5 s (26 cycles) < SCL release time 3.25 s (13 cycles) < Setup time 3.25 s (13 cycles) < Hold time High-speed Clock Mode 1.0 s (4 cycles) < SCL release time 0.5 s (2 cycles) < Setup time 0.5 s (2 cycles) < Hold time
Note: Absolute time at = 4 MHz. The value in parentheses denotes the number of cycles.
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8.6.10 Example of Master Transmission
An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz and in the ACK return mode is shown below. Set a slave address in the high-order 7 bits of the I2C address register (address 00F716) and "0" in the RBW bit. Set the ACK return mode and SCL = 100 kHz by setting "8516" in the I2C clock control register (address 00FA16). Set "1016" in the I2C status register (address 00F816) and hold the SCL at the HIGH. Set a communication enable status by setting "4816" in the I2C control register (address 00F916). Set the address data of the destination of transmission in the highorder 7 bits of the I2C data shift register (address 00F616) and set "0" in the least significant bit. Set "F016" in the I2C status register (address 00F816) to generate a START condition. At this time, an SCL for 1 byte and an ACK clock automatically occurs. Set transmit data in the I2C data shift register (address 00F616). At this time, an SCL and an ACK clock automatically occurs. When transmitting control data of more than 1 byte, repeat step . Set "D016" in the I2C status register (address 00F816). After this, if ACK is not returned or transmission ends, a STOP condition will be generated.
8.6.11 Example of Slave Reception
An example of slave reception in the high-speed clock mode, at the SCL frequency of 400 kHz, in the ACK non-return mode, using the addressing format, is shown below. Set a slave address in the high-order 7 bits of the I 2C address register (address 00F716) and "0" in the RBW bit. Set the no ACK clock mode and SCL = 400 kHz by setting "2516" in the I2C clock control register (address 00FA16). Set "1016" in the I2C status register (address 00F816) and hold the SCL at the HIGH. Set a communication enable status by setting "4816" in the I2C control register (address 00F916). When a START condition is received, an address comparison is made. *When all transmitted address are"0" (general call): AD0 of the I2C status register (address 00F816) is set to "1"and an interrupt request signal occurs. *When the transmitted addresses match the address set in : ASS of the I2C status register (address 00F816) is set to "1" and an interrupt request signal occurs. *In the cases other than the above: AD0 and AAS of the I2C status register (address 00F816) are set to "0" and no interrupt request signal occurs. Set dummy data in the I2C data shift register (address 00F616). When receiving control data of more than 1 byte, repeat step . When a STOP condition is detected, the communication ends.
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S
Slave address R/W
A
Data
A
Data
A/A
P
7 bits "0" 1 to 8 bits 1 to 8 bits (1) A master-transmitter transmits data to a slave-receiver
S
Slave address R/W
A
Data
A
Data
A
P
7 bits "1" 1 to 8 bits 1 to 8 bits (2) A master-receiver receives data from a slave-transmitter Slave address R/W 1st 7 bits Slave address 2nd byte
S
A
A
Data
A
Data
A/A
P
7 bits "0" 8 bits 1 to 8 bits 1 to 8 bits (3) A master-transmitter transmits data to a slave-receiver with a 10-bit address Slave address R/W 1st 7 bits Slave address 2nd byte Slave address R/W 1st 7 bits
S
A
A
Sr
Data
A
Data 1 to 8 bits
A
P
7 bits "0" 8 bits 7 bits "1" 1 to 8 bits (4) A master-receiver receives data from a slave-transmitter with a 10-bit address S : START condition A : ACK bit Sr : Restart condition P : STOP condition R/W : Read/Write bit From master to slave From slave to master
Fig. 8.6.12 Address Data Communication Format
8.6.12 Precautions when using multi-master I2C BUS interface
(1) Read-modify-write instruction The precautions when the raead-modify-write instruction such as SEB, CLB etc. is executed for each register of the multi-master I2C-BUS interface are described below. *I2C data shift register (S0) When executing the read-modify-write instruction for this register during transfer, data may become a value not intended. *I2C address register (S0D) When the read-modify-write instruction is executed for this register at detecting the STOP condition, data may become a value not ______ intended. It is because hardware changes the read/write bit (RBW) at the above timing. *I2C status register (S1) Do not execute the read-modify-write instruction for this register because all bits of this register are changed by hardware. *I2C control register (S1D) When the read-modify-write instruction is executed for this register at detecting the START condition or at completing the byte transfer, data may become a value not intended. Because hardware changes the bit counter (BC0-BC2) at the above timing. *I2C clock control register (S2) The read-modify-write instruction can be executed for this register.
(2) START condition generating procedure using multi-master Procedure example (The necessary conditions of the generating procedure are described as the following to ). * * --
LDA SEI BBS 5,S1,BUSBUSY BUSFREE: STA S0 LDM #$F0, S1 CLI * * BUSBUSY: CLI * *
(Taking out of slave address value) (Interrupt disabled) (BB flag confirming and branch process) (Writing of slave address value) (Trigger of START condition generating) (Interrupt enabled)
(Interrupt enabled)
Use "STA," "STX" or "STY" of the zero page addressing instruction for writing the slave address value to the I2C data shift register. Use "LDM" instruction for setting trigger of START condition generating. Write the slave address value of above and set trigger of START condition generating of above continuously shown the above procedure example. Disable interrupts during the following three process steps: * BB flag confirming * Writing of slave address value * Trigger of START condition generating When the condition of the BB flag is bus busy, enable interrupts immediately.
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(3) RESTART condition generating procedure Procedure example (The necessary conditions of the generating procedure are described as the following to .) Execute the following procedure when the PIN bit is "0." * * #$00, S1 -- S0 #$F0, S1 * * Select the slave receive mode when the PIN bit is "0." Do not write "1" to the PIN bit. Neither "0" nor "1" is specified for the writing to the BB bit. The TRX bit becomes "0" and the SDA pin is released. The SCL pin is released by writing the slave address value to the I2C data shift register. Use "STA," "STX" or "STY" of the zero page addressing instruction for writing. Use "LDM" instruction for setting trigger of RESTART condition generating. Write the slave address value of above and set trigger of RESTART condition generating of above continuously shown the above procedure example. Disable interrupts during the following two process steps: * Writing of slave address value * Trigger of RESTART condition generating
(4) STOP condition generating procedure Procedure example (The necessary conditions of the generating procedure are described as the following to .) * *
LDM LDA SEI STA LDM CLI
(Select slave receive mode) (Taking out of slave address value) (Interrupt disabled) (Writing of slave address value) (Trigger of RESTART condition generating) (Interrupt enabled)
SEI LDM #$C0, S1 NOP LDM #$D0, S1 CLI * *
(Interrupt disabled) (Select master transmit mode) (Set NOP) (Trigger of STOP condition generating) (Interrupt enabled)
Write "0" to the PIN bit when master transmit mode is select. Execute "NOP" instruction after setting of master transmit mode. Also, set trigger of STOP condition generating within 10 cycles after selecting of master trasmit mode. Disable interrupts during the following two process steps: * Select of master transmit mode * Trigger of STOP condition generating (5) Writing to I2C status register Do not execute an instruction to set the PIN bit to "1" from "0" and an instruction to set the MST and TRX bits to "0" from "1" simultaneously. It is because it may enter the state that the SCL pin is released and the SDA pin is released after about one machine cycle. Do not execute an instruction to set the MST and TRX bits to "0" from "1" simultaneously when the PIN bit is "1." It is because it may become the same as above. (6) Process of after STOP condition generating Do not write data in the I2C data shift register S0 and the I2C status register S1 until the bus busy flag BB becomes "0" after generating the STOP condition in the master mode. It is because the STOP condition waveform might not be normally generated. Reading to the above registers do not have the problem.
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8.7 PWM OUTPUT CIRCUIT
This microcomputer is equipped with eight 8-bit PWMs (PWM0- PWM7). PWM0-PWM7 have the same circuit structure and an 8-bit resolution with minimum resolution bit width of 4 s and repeat period of 1024 s (for f(XIN) = 8 MHz) . Figure 8.7.1 shows the PWM block diagram. The PWM timing generating circuit applies individual control signals to PWM0-PWM7 using f(XIN) divided by 2 as a reference signal.
8.7.1 Data Setting
When outputting PWM0-PWM7, set 8-bit output data to the PWMi register (i means 0 to 7; addresses 020016 to 020716).
8.7.2 Transmitting Data from Register to PWM circuit
Data transfer from the PWM register to the PWM circuit is executed at writing data to the register. The signal output from the PWM output pin corresponds to the contents of this register.
8.7.3 PWM Operation
The following explains PWM operation. First, set the bit 0 of PWM mode register 1 (address 020A16) to "0" (at reset, bit 0 is already set to "0" automatically), so that the PWM count source is supplied. PWM0-PWM3 are also used as pins P04-P07, PWM4-PWM6 are also used as pins P00-P02, and PWM7 is also used as pin P50 and P03 respectively. Set the corresponding bits of the port P0 direction register to "1" (output mode). And select each output polarity by bit 3 of PWM mode register 1 (address 020A16). Then, set bits 7 to 0 of PWM mode register 2 to "1" (PWM output). The PWM waveform is output from the PWM output pins by setting these registers. Figure 8.7.2 shows the PWM timing. One cycle (T) is composed of 256 (28) segments. The 8 kinds of pulses, relative to the weight of each bit (bits 0 to 7), are output inside the circuit during 1 cycle. Refer to Figure 8.7.2 (a). The PWM outputs waveform which is the logical sum (OR) of pulses corresponding to the contents of bits 0 to 7 of the PWM register. Several examples are shown in Figure 8.7.2 (b). 256 kinds of output (HIGH area: 0/256 to 255/256) are selected by changing the contents of the PWM register. A length of entirely HIGH cannot be output, i.e. 256/256.
8.7.4 Output after Reset
At reset, the output of port P0 is in the high-impedance state, port P50 outputs Low, and the contents of the PWM register and the PWM circuit are undefined. Note that after reset, the PWM output is undefined until setting the PWM register.
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Data bus PWM timing generating circuit PN0 PWM0 register (Address 020016) b7
8
XIN
1/2
b0
POL PWM circuit
P04 PW0 P05 PW1 P06 PW2 P07 PW3 P00 PW4 P01 PW5 P02 PW6 P50 PW7 D03 P03
D04
PWM0
D05
PWM1
PWM1 register (Address 020116)
D06
PWM2
PWM2 register (Address 020216)
D07
PWM3
PWM3 register (Address 020316)
D00
PWM4
PWM4 register (Address 020416)
D01
PWM5
PWM5 register (Address 020516)
D02
PWM6
PWM6 register (Address 020616)
PWM7
PWM7 register (Address 020716)
Selection gate: Connected to black side at reset. Inside of is as same contents with the others.
PWM7
PN4 PN : PWM mode register 1 [address 020A16] PW : PWM mode register 2 [address 020B16] P0 : Port P0 register [address 00C016] D0 : Port P0 direction register [address 00C116]
Fig. 8.7.1 PWM Block Diagram
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1 3579 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 255
20
30
40
50
Bit 7
54 58 62 66 70 74 78 82 86 90 94 98 102 106 110 114 118 122 126 130 134 138 142 146 150 154 158 162 166 170 174 178 182 186 190 194 198 202 206 210 214 218 222 226 230 234 238 242 246 250 254
Fig. 8.7.2 PWM Timing
52 60 68 76 84 92 100 108 116 124 132 140 148 156 164 172 180 188 196 204 212 220 228 236 244 252 56 72 88 104 120 136 152 168 184 200 216 232 248 80 112 144 176 208 240 96 160 224 64 192 128
2
6 10 14
18
22
26
30 34 38
42
46 50
Bit 6
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(a) Pulses showing the weight of each bit T = 256 t PWM output t = 4 s T = 1024 s f(XIN) = 8 MHz (b) Example of 8-bit PWM
4
12
20
28
36
44
Bit 5
8
24
40
Bit 4
16
48
Bit 3
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32
Bit 2
Bit 1
Bit 0
0016 (0)
0116 (1)
1816 (24)
FF16 (255)
t
M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
PWM Mode Register 1
b7 b6 b5 b4 b3 b2 b1 b0 PWM mode register 1 (PN) [Address 020A16] B 0 Name PWM counts source selection bit (PN0) Functions 0 : Count source supply 1 : Count source stop After reset 0 0 0 0 0 RW RW R-- RW RW R--
1, 2 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0." 3 4 PWM output polarity selection bit (PN3) P03/PWM7 output selection bit (PN4) 0 : Positive polarity 1 : Negative polarity 0 : P03 output 1 : PWM7 output
5 to 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0."
Fig. 8.7.3 PWM Mode Register 1
PWM Mode Register 2
b7 b6 b5 b4 b3 b2 b1 b0 PWM mode register 2 (PW) [Address 020B16] B Name 0 P04/PWM0 output selection bit (PW0) 1 P05/PWM1 output selection bit (PW1) 2 P06/PWM2 output selection bit (PW2) 3 P07/PWM3 output selection bit (PW3) 4 P00/PWM4 output selection bit (PW4) 5 P01/PWM5 output selection bit (PW5) 6 P02/PWM6 output selection bit (PW6) 7 P50/PWM7 output selection bit (PW7) Functions 0 : P04 output 1 : PWM0 output 0 : P05 output 1 : PWM1 output 0 : P06 output 1 : PWM2 output 0 : P07 output 1 : PWM3 output 0 : P00 output 1 : PWM4 output 0: P01 output 1: PWM5 output 0: P02 output 1: PWM6 output 0: P50 output 1: PWM7 output After reset R W 0 RW 0 0 0 0 0 0 0 RW RW RW RW RW RW RW
Fig. 8.7.4 PWM Mode Register 2
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
8.8 A-D CONVERTER 8.8.1 A-D Conversion Register (AD)
A-D conversion reigister is a read-only register that stores the result of an A-D conversion. This register should not be read during A-D conversion.
8.8.3 Comparison Voltage Generator (Resistor Ladder)
The voltage generator divides the voltage between VSS and VCC by 256, and outputs the divided voltages to the comparator as the reference voltage Vref.
8.8.2 A-D Control Register (ADCON)
The A-D control register controls A-D conversion. Bits 2 to 0 of this register select analog input pins. When these pins are not used as anlog input pins, they are used as ordinary I/O pins. Bit 3 is the A-D conversion completion bit, A-D conversion is started by writing "0" to this bit. The value of this bit remains at "0" during an A-D conversion, then changes to "1" when the A-D conversion is completed. Bit 4 controls connection between the resistor ladder and VCC. When not using the A-D converter, the resistor ladder can be cut off from the internal VCC by setting this bit to "0," accordingly providing lowpower dissipation.
8.8.4 Channel Selector
The channel selector connects an analog input pin, selected by bits 2 to 0 of the A-D control register, to the comparator.
8.8.5 Comparator and Control Circuit
The conversion result of the analog input voltage and the reference voltage "Vref" is stored in the A-D conversion register. The A-D conversion completion bit and A-D conversion interrupt request bit are set to "1" at the completion of A-D conversion.
Data bus
b7 A-D control register (address 00EF16) 3
b0
A-D control circuit AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 VSS VCC Comparator A-D conversion register 8 (address 00EE16)
A-D conversion interrupt request
Channel selector
Switch tree
Resistor ladder
Fig. 8.8.1 A-D Comparator Block Diagram
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A-D Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
A-D control register (ADCON) [Address 00EF16]
B
0 to 2
Name
Analog input pin selection bits (ADIN0 to ADIN2) b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1
Functions
b0 0 : AD1 1 : AD2 0 : AD3 1 : AD4 0 : AD5 1 : AD6 0 : AD7 1 : AD8
After reset R W
0
RW
3 4 5 6 7
A-D conversion completion bit (ADSTR) VCC connection selection bit (ADVREF) Fix this bit to "0."
0: Conversion in progress 1: Convertion completed 0: OFF 1: ON
1 0 0 Indeterminate
RW RW RW R-- RW
Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is indeterminate. Fix this bit to "0."
0
Fig. 8.8.2 A-D Control Register
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8.8.6 Conversion Method
Set bit 7 of the interrupt input polarity register (address 021216) to "1" to generate an interrupt request at completion of A-D conversion. Set the A-D conversion * INT3 interrupt request bit to "0" (even when A-D conversion is started, the A-D conversion * INT3 interrupt reguest bit is not set to "0" automatically). When using A-D conversion interrupt, enable interrupts by setting A-D conversion * INT3 interrupt request bit to "1" and setting the interrupt disable flag to "0." Set the VCC connection selection bit to "1" to connect VCC to the resistor ladder. Select analog input pins by the analog input selection bit of the AD control register. Set the A-D conversion completion bit to "0." This write operation starts the A-D conversion. Do not read the A-D conversion register during the A-D conversion. Verify the completion of the conversion by the state ("1") of the A-D conversion completion bit, the state ("1") of A-D conversion * INT3 interrupt reguest bit, or the occurrence of an A-D conversion interrupt. Read the A-D conversion register to obtain the conversion results.
Note : When the ladder resistor is disconnect from VCC, set the VCC connection selection bit to "0" between steps and .
8.8.7 Internal Operation
When the A-D conversion starts, the following operations are automatically performed. The A-D conversion register is set to "0016." The most significant bit of the A-D conversion register becomes "1, " and the comparison voltage "Vref" is input to the comparator. At this point, Vref is compared with the analog input voltage "VIN ." Bit 7 is determined by the comparison results as follows. When Vref < VIN : bit 7 holds "1" When Vref > VIN : bit 7 becomes "0" With the above operations, the analog value is converted into a digital value. The A-D conversion terminates in a maximum of 50 machine cycles (12.5 s at f(XIN) = 8 MHz) after it starts, and the conversion result is stored in the A-D conversion register. An A-D conversion interrupt request occurs at the same time as A-D conversion completion, the A-D conversion * INT3 interrupt request bit becomes "1." The A-D conversion completion bit also becomes "1."
Table 8.8.1 Expression for Vref and VREF A-D conversion register contents "n" (decimal notation) 0 1 to 255
Note: VREF indicates the reference voltage (= Vcc).
Vref (V) 0 VREF (n - 0.5) 256
Contents of A-D conversion register A-D conversion start
Reference voltage (Vref) [V]
00000
000
0
VREF VREF - 2 512 VREF VREF VREF - 2 4 512 VREF VREF VREF VREF - 2 4 8 512 VREF VREF VREF ..... 2 4 8 ....... VREF - VREF 512 256
1st comparison start 2nd comparison start 3rd comparison start
10000000 11000000 12100000 12345671
8th comparison start
A-D conversion completion (8th comparison completion)
12345678
Digital value corresponding to analog input voltage.
m
: Value determined by mth (m = 1 to 8) result
Fig. 8.8.3 Changes in A-D Conversion Register and Comparison Voltage during A-D Conversion
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8.8.8 Definition of A-D Conversion Accuracy
The definition of A-D conversion accuracy is described below (refer to Figure 8.8.4). (1) Relative Accuracy *Zero transition error (V0T) The deviation of the input voltage at which A-D conversion output data changes from "0" to "1," from the corresponding ideal A-D conversion characteristics between 0 and VREF. V0T = (V0 - 1/2 VREF/256) 1LSB [LSB]
* EDifferential non-linearity error The deviation of the input voltage required to change output data by "1," from the corresponding ideal A-D conversion characteristics between 0 and VREF. (Vn+1 - Vn) - 1LSB 1LSB
Differential non-linearity error =
[LSB]
(2) Absolute Accuracy * EAbsolute accuracy error The deviation of the actual A-D conversion characteristics, from the ideal A-D conversion characteristics between 0 and VREF. Vn - 1LSBA (n + 1/2) Absolute accuracy error = 1LSBA [LSB]
* Full-scale transition error (VFST) The deviation of the input voltage at which A-D conversion output data changes from "255" to "254," from the corresponding ideal AD conversion characteristics between 0 and VREF. VFST = (VREF - 3/2 VREF/256) - V254 1LSB [LSB]
Note: The analog input voltage "Vn" at which A-D conversion output data changes from "n" to "n + 1" (n ; 0 to 254) is as follows (refer to Figure 8.8.4) :
* Non-linearity error The deviation of the actual A-D conversion characteristics, from the ideal A-D conversion characteristics between V0 and V254. Vn - (1LSB n + V0) 1LSB
1LSB with respect to relative accuracy =
V254 - V0 254 VREF [V]
Non-linearity error =
[LSB]
1LSBA with respect to absolute accuracy =
256
[V]
Output code 0916 0816 Absolute accuracy 0716 0616 0516 0416 0316 - 2LSB 0216 0116 0016 0 20 40 60 80 100 120 140 160 180 200 220 Analog input voltage (mV) + 2LSB Ideal A-D conversion characteristics Limitless resolution A-D conversion characteristics
Fig. 8.8.4 Definition of A-D Conversion Accuracy
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8.9 ROM CORRECTION FUNCTION
This can correct program data in ROM. Up to 2 addresses can be corrected, a program for correction is stored in the ROM correction vector in RAM as the top address. The ROM memory for correction vectors are vectors. Vector 1 : address 02C016 Vector 2 : address 02E016 Set the address of the ROM data to be corrected into the ROM correction address register. When the value of the counter matches the ROM data address in the ROM correction vector as the top address, the main program branches to the correction program stored in the ROM memory for correction. To return from the correction program to the main program, the op code and operand of the JMP instruction (total of 3 bytes) are necessary at the end of the correction program. The ROM correction function is controlled by the ROM correction enable register.
Notes 1: Specify the first address (op code address) of each instruction as the ROM correction address. 2: Use the JMP instruction (total of 3 bytes) to return from the correction program to the main program. 3: Do not set the same ROM correction address to vector 1 and 2. 4: For the M37280MKH-XXXSP and M37280EKSP, when using the expansion ROM (BK7 = "1"), the ROM correction function do not operate used for addresses 100016 to1FFF16. Note that on programming.
ROM correction address 1 (high-order) 020C16 ROM correction address 1 (low-order) 020D16
ROM correction address 2 (high-order) 020E16 ROM correction address 2 (low-order) 020F16
Fig. 8.9.1 ROM Correction Address Registers
ROM Correction Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
00
ROM correction enable register (RCR) [Address 021016] B
0 1
Name
Vector 1 enable bit (RCR0) Vector 2 enable bit (RCR1)
Functions
0: Disabled 1: Enabled 0: Disabled 1: Enabled
After reset R W
0 0
RW RW RW R--
2, 3 Fix these bits to "0."
0
4 to 7
Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0."
0
Fig. 8.9.2 ROM Correction Enable Register
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8.10 DATA SLICER
This microcomputer includes the data slicer function for the closed caption decoder (referred to as the CCD). This function takes out the caption data superimposed in the vertical blanking interval of a composite video signal. A composite video signal which makes the sync chip's polarity negative is input to the CVIN pin.
When the data slicer function is not used, the data slicer circuit and the timing signal generating circuit can be cut off by setting bit 0 of the data slicer control register 1 (address 00E016) to "0." These settings can realize the low-power dissipation.
Composite video signal
0.1 F 1 M
470 560 pF 1 F
1 k 200 pF Sync pulse counter register (address 00E916) HLF
CVIN
HSYNC
Synchronizing signal counter Clamping circuit Low-pass filter Sync slice circuit
Synchronizing separation circuit
Data slicer control register 2 (address 00E116)
Data slicer control register 1 (address 00E016) Timing signal generating circuit
Data slicer ON/OFF
Reference voltage generating 1000 pF circuit
VHOLD
+ - Comparator
Clock run-in determination circuit
Data slice line specification circuit
Clock run-in defect register (address 00EA16)
Start bit detecting circuit
External circuit Note : Make the length of wiring which is connected to VHOLD, HLF, and CVIN pin as short as possible so that a leakage current may not be generated when mounting a resistor or a capacitor on each pin.
Caption position register (address 00E616)
Data clock generating circuit Data clock position register (address 00EB16) 16-bit shift register Interrupt request generating circuit
high-order low-order Caption data register 1 (address 00E216)
Data slicer interrupt request
Caption data register 2 (address 00E316)
Caption data register 4 (address 00E516)
Caption data register 3 (address 00E416)
Data bus
Fig. 8.10.1 Data Slicer Block Diagram
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8.10.1 Notes When not Using Data Slicer
When bit 0 of data slicer control register 1 (address 00E016) is "0," terminate the pins as shown in Figure 8.10.2.

Apply the same voltage as VCC to AVCC pin.
()
24
AVCC
Apply HLF pin VCC or VSS level. Apply VHOLD pin VCC or VSS level. Pull-up CVIN pin to VCC through a resistor of 5 k or more.
VCC or VSS VCC or VSS
25 27
HLF VHOLD
VCC or VSS
28
CVIN
() Only M37280EKSP have AVCC pin. This pin is non-connection pin in M37280MFH-XXXSP, M37280MKH-XXXSP. But NC pin of M37280MFH-XXXSP, M37280MKH-XXXSP is not connect in the IC. You can apply to Vcc.
Fig. 8.10.2 Termination of Data Slicer Input/Output Pins when Data Slicer Circuit and Timing Generating Circuit Is in OFF State
When both bits 0 and 2 of data slicer control register 1 (address 00E016) are "1," terminate the pins as shown in Figure 8.10.3.

Apply the same voltage as VCC to AVCC pin.
()
24 1 k
AVCC
Connect the same external circuit as when using data slicer to HLF pin. Leave VHOLD pin open. Pull-up CVIN to VCC through a resistor of 5 k or more.
1 F
25 200pF
HLF
Open
27
VHOLD
5 k or more
28
CVIN
() Only M37280EKSP have AVCC pin. This pin is non-connection pin in M37280MFH-XXXSP, M37280MKH-XXXSP. But NC pin of M37280MFH-XXXSP, M37280MKH-XXXSP is not connect in the IC. You can apply to Vcc.
Fig. 8.10.3 Termination of Data Slicer Input/Output Pins when Timing Signal Generating Circuit Is in ON State
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Figures 8.10.4 and 8.10.5 the data slicer control registers.
Data Slicer Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0 00000 Data slicer control register 1(DSC1) [Address 00E016] B Name Functions 0: Stopped 1: Operating 0: F2 1: F1 0: Video signal 1: HSYNC signal After reset R W 0 0 0 0 RW RW RW RW
0 Data slicer and timing signal generating circuit control bit (DSC10) 1 Selection bit of data slice reference voltage generating field (DSC11) 2 Reference clock source selection bit (DSC12) 3 to Fix these bits to "0." 7
Definition of fields 1 (F1) and 2 (F2) F1: Hsep Vsep F2: Hsep Vsep
Fig. 8.10.4 Data Slicer Control Register 1
Data Slicer Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Data slicer control register 2 (DSC2) [Address 00E116]
B 0
Name Caption data latch completion flag 1 (DSC20)
Functions
After reset
RW
0: Data is not latched yet and a Indeterminate R -- clock-run-in is not determined. 1: Data is latched and a clock-run-in is determined. 0 Read-only 0: F2 1: F1 0: Method (1) 1: Method (2) RW
1 2 3 4
Fix this bit to "0." Test bit Field determination flag(DSC23) Vertical synchronous signal (Vsep) generating method selection bit (DSC24)
Indeterminate R -- Indeterminate R -- 0 RW
5 6 7
0: Match V-pulse shape determination flag (DSC25) 1: Mismatch Fix this bit to "0." Test bit Read-only
Indeterminate R -- 0 RW
Indeterminate R --
Definition of fields 1 (F1) and 2 (F2) F1: Hsep Vsep F2: Hsep Vsep
Fig. 8.10.5 Data Slicer Control Register 2
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8.10.2 Clamping Circuit and Low-pass Filter
The clamp circuit clamps the sync chip part of the composite video signal input from the CVIN pin. The low-pass filter attenuates the noise of clamped composite video signal. The CVIN pin to which composite video signal is input requires a capacitor (0.1 F) coupling outside. Pull down the CVIN pin with a resistor of hundreds of kiloohms to 1 M. In addition, we recommend to install externally a simple lowpass filter using a resistor and a capacitor at the CVIN pin (refer to Figure 8.10.1).
Composite s Measure "L" period Timing signal
8.10.3 Sync Slice Circuit
This circuit takes out a composite sync signal from the output signal of the low-pass filter.
Vsep signal
8.10.4 Synchronous Signal Separation Circuit
This circuit separates a horizontal synchronous signal and a vertical synchronous signal from the composite sync signal taken out in the sync slice circuit. (1)Horizontal Synchronous Signal (Hsep) A one-shot horizontal synchronizing signal Hsep is generated at the falling edge of the composite sync signal. (2)Vertical Synchronous Signal (Vsep) As a Vsep signal generating method, it is possible to select one of the following 2 methods by using bit 4 of the data slicer control register 2 (address 00E116). *Method 1 The "L" level width of the composite sync signal is measured. If this width exceeds a certain time, a Vsep signal is generated in synchronization with the rising of the timing signal immediately after this "L" level. *Method 2 The "L" level width of the composite sync signal is measured. If this width exceeds a certain time, it is detected whether a falling of the composite sync signal exits or not in the "L" level period of the timing signal immediately after this "L" level. If a falling exists, a Vsep signal is generated in synchronization with the rising of the timing signal (refer to Figure 8.10.6). Figure 8.10.6 shows a Vsep generating timing. The timing signal shown in the figure is generated from the reference clock which the timing generating circuit outputs. Reading bit 5 of data slicer control register 2 permits determinating the shape of the V-pulse portion of the composite sync signal. As shown in Figure 8.10.7, when the A level matches the B level, this bit is "0." In the case of a mismatch, the bit is "1."
A Vsep signal is generated at a rising of the timing signal immediately after the "L" level width of the composite sync signal exceeds a certain time.
Fig. 8.10.6 Vsep Generating Timing (method 2)
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8.10.5 Timing Signal Generating Circuit
This circuit generates a reference clock which is 832 times as large as the horizontal synchronous signal frequency. It also generates various timing signals on the basis of the reference clock, horizontal synchronous signal and vertical synchronizing signal. The circuit operates by setting bit 0 of data slicer control register 1 (address 00E016) to "1." The reference clock can be used as a display clock for OSD function in addition to the data slicer. The HSYNC signal can be used as a count source instead of the composite sync signal. However, when the HSYNC signal is selected, the data slicer cannot be used. A count source of the reference clock can be selected by bit 2 of data slicer control register 1 (address 00E016). For the pins HLF, connect a resistor and a capacitor as shown in Figure 8.10.1. Make the length of wiring which is connected to these pins as short as possible so that a leakage current may not be generated.
Note: It takes a few tens of milliseconds until the reference clock becomes stable after the data slicer and the timing signal generating circuit are started. In this period, various timing signals, Hsep signals and Vsep signals become unstable. For this reason, take stabilization time into consideration when programming.
Bit 5 of DSC2 0 Composite sync signal 1 1 A B
Fig. 8.10.7 Determination of V-pulse Waveform
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8.10.6 Data Slice Line Specification Circuit
(1) Specification of Data Slice Line This circuit decides a line on which caption data is superimposed. The line 21 (fixed), 1 appropriate line for a period of 1 field (total 2 line for a period of 1 field), and both fields (F1 and F2) are sliced their data. The caption position register (address 00E616) is used for each setting (refer to Table 8.10.1). The counter is reset at the falling edge of Vsep and is incremented by 1 every Hsep pulse. When the counter value matched the value specified by bits 4 to 0 of the caption position register, this Hsep is sliced. The values of "0016" to "1F16" can be set in the caption position register (at setting only 1 appropriate line). Figure 8.10.8 shows the signals in the vertical blanking interval. Figure 8.10.9 shows the structure of the caption position register. (2) Specification of Line to Set Slice Voltage The reference voltage for slicing (slice voltage) is generated for the clock run-in pulse in the particular line (refer to Table 7). The field to generate slice voltage is specified by bit 1 of data slicer control register 1. The line to generate slice voltage 1 field is specified by bits 6, 7 of the caption position register (refer to Table 8.10.1).
(3) Field Determination The field determination flag can be read out by bit 3 of data slicer control register 2. This flag charge at the falling edge of Vsep.
Video signal
Vertical blanking interval
Composite video signal Vsep
1 appropriate line is set by the caption position register Line 21 (when setting line 19)
Hsep
Count value to be set in the caption position register ("0F16" in this case)
Magnified drawing
Hsep Clock run-in Start bit + 16-bit data
Composite video signal Window for deteminating clock-run-in
Start bit
Fig. 8.10.8 Signals in Vertical Blanking Interval
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Caption Position Register
b7 b6 b5 b4 b3 b2 b1 b0 Caption Position Register (CPS) [Address 00E616]
B 0 to 4 5
Name Caption position bits(CPS0 to CPS4) Caption data latch completion flag 2 (CPS5)
Functions
After reset 0
RW RW
0: Data is not latched yet and a Indeterminate R -- clock-run-in is not determined. 1: Data is latched and a clock-run-in is determined. Refer to the corresponding Table (Table 12.10.1). 0 RW
6, 7 Slice line mode specification bits (in 1 field) (CPS6, CPS7)
Fig. 8.10.9 Caption Position Register
Table 8.10.1 Specification of Data Slice Line CPS b7 0 b6 0 Field and Line to Be Sliced Data * Both fields of F1 and F2 * Line 21 and a line specified by bits 4 to 0 of CPS (total 2 lines) (See note 2) * Both fields of F1 and F2 * A line specified by bits 4 to 0 of CPS (total 1 line) (See note 3) * Both fields of F1 and F2 * Line 21 (total 1 line) * Both fields of F1 and F2 * Line 21 and a line specified by bits 4 to 0 of CPS (total 2 lines) (See note 2) Field and Line to Generate Slice Voltage * Field specified by bit 1 of DSC1 * Line 21 (total 1 line) * Field specified by bit 1 of DSC1 * A line specified by bits 4 to 0 of CPS (total 1 line) (See note 3) * Field specified by bit 1 of DSC1 * Line 21 (total 1 line) * Field specified by bit 1 of DSC1 * Line 21 and a line specified by bits 4 to 0 of CPS (total 2 lines) (See note 2)
0 1 1
1 0 1
Notes 1: DSC1 is data slicer control register 1. CPS is caption position register. 2: Set "0016" to "1016" to bits 4 to 0 of CPS. 3: Set "0016" to "1F16" to bits 4 to 0 of CPS.
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8.10.7 Reference Voltage Generating Circuit and Comparator
The composite video signal clamped by the clamping circuit is input to the reference voltage generating circuit and the comparator. (1) Reference Voltage Generating Circuit This circuit generates a reference voltage (slice voltage) by using the amplitude of the clock run-in pulse in line specified by the data slice line specification circuit. Connect a capacitor between the VHOLD pin and the VSS pin, and make the length of wiring as short as possible so that a leakage current may not be generated. (2) Comparator The comparator compares the voltage of the composite video signal with the voltage (reference voltage) generated in the reference voltage generating circuit, and converts the composite video signal into a digital value.
8.10.8 Start Bit Detecting Circuit
This circuit detects a start bit at line decided in the data slice line specification circuit. The detection of a start bit is described below. A sampling clock is generated by dividing the reference clock output by the timing signal. A clock run-in pulse is detected by the sampling clock. After detection of the pulse, a start bit pattern is detected from the comparator output.
8.10.9 Clock Run-in Determination Circuit
This circuit determinates clock run-in by counting the number of pulses in a window of the composite video signal. The reference clock count value in one pulse cycle is stored in bits 3 to 7 of the clock run-in detect register (address 00EA16). Read out these bits after the occurrence of a data slicer interrupt (refer to "8.10.12 Interrupt Request Generating Circuit"). Figure 8.10.10 shows the structure of clock run-in detect register.
Clock Run-in Detect Register
b7 b6 b5 b4 b3 b2 b1 b0 Clock run-in detect register (CRD) [Address 00EA16]
B 0 to 2 3 to 7 Test bits
Name Read-only
Functions
After reset R W 0 R--
Clock run-in detection bit(CRD3 to CRD7)
Number of reference clocks to be counted in one clock run-in pulse period.
0
R--
Fig. 8.10.10 Clock Run-in Detect Register
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8.10.10 Data Clock Generating Circuit
This circuit generates a data clock synchronized with the start bit detected in the start bit detecting circuit. The data clock stores caption data to the 16-bit shift register. When the 16-bit data has been stored and the clock run-in determination circuit determines clock run-in, the caption data latch completion flag is set. This flag is reset at a falling of the vertical synchronous signal (Vsep).
Data Clock Position Register
b7 b6 b5 b4 b3 b2 b1 b0 0 0 1 Data clock position register (DPS) [Address 00EB16]
B 0
Name Fix these bits to "1."
Functions
After reset R W 1 0 1 0 RW RW RW
1,2 Fix this bit to "0." 3 4 to 7 Data clock position set bits (DPS3 to DPS7)
Fig. 8.10.11 Data Clock Position Register
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8.10.11 16-bit Shift Register
The caption data converted into a digital value by the comparator is stored into the 16-bit shift register in synchronization with the data clock. The contents of the high-order 8 bits of the stored caption data can be obtained by reading out data register 2 (address 00E316) and data register 4 (address 00E516). The contents of the low-order 8 bits can be obtained by reading out data register 1 (address 00E216) and data register 3 (address 00E416), respectively. These registers are reset to "0" at a falling of Vsep. Read out data registers 1 and 2 after the occurrence of a data slicer interrupt (refer to "8.10.12 Interrupt Request Generating Circuit").
8.10.12 Interrupt Request Generating Circuit
The interrupt requests as shown in Table 8.10.3 are generated by combination of the following bits; bits 6 and 7 of the caption position register (address 00E616). Read out the contents of data registers 1 to 4 and the contents of bits 3 to 7 of the clock run-in detect register after the occurrence of a data slicer interrupt request.
Table 8.10.2 Contents of Caption Data Latch Completion Flag and 16-bit Shift Register Slice Line Specification Mode CPS bit 7 bit 6 0 0 1 1 0 1 0 1 Contents of Caption Data Latch Completion Flag Completion Flag 1 (bit 0 of DSC2) Line 21 A line specified by bits 4 to 0 of CPS Line 21 Line 21 Completion Flag 2 (bit 5 of CPS) A line specified by bits 4 to 0 of CPS Invalid Invalid A line specified by bits 4 to 0 of CPS Contents of 16-bit Shift Register Caption Data Registers 1, 2 16-bit data of line 21 16-bit data of a line specified by bits 4 to 0 of CPS 16-bit data of line 21 16-bit data of line 21 Caption Data Registers 3, 4 16-bit data of a line specified by bits 4 to 0 of CPS Invalid Invalid 16-bit data of a line specified by bits 4 to 0 of CPS
CPS: Caption position register DSC2: Data slicer control register 2
Table 8.10.3 Occurence Sources of Interrupt Request Caption position register b7 b6 0 0 1 0 1 1 Occurence Souces of Interrupt Request at End of Data Slice Line After slicing line 21 After a line specified by bits 4 to 0 of CPS After slicing line 21 After slicing line 21
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8.10.13 Synchronous Signal Counter
The synchronous signal counter counts the composite sync signal taken out from a video signal in the data slicer circuit or the vertical synchronous signal Vsep as a count source. The count value in a certain time (T time) generated by f(XIN)/213 or f(XIN)/213 is stored into the 5-bit latch. Accordingly, the latch value changes in the cycle of T time. When the count value exceeds "1F16," "1F16" is stored into the latch.
The latch value can be obtained by reading out the sync pulse counter register (address 00E916). A count source is selected by bit 5 of the sync pulse counter register. The synchronous signal counter is used when bit 0 of PWM mode register 1 (address 020816). Figure 8.10.12 shows the structure of the sync pulse counter and Figure 8.10.13 shows the synchronous signal counter block diagram.
Sync Signal Counter Register
b7 b6 b5 b4 b3 b2 b1 b0 Sync pulse counter register (HC) [Address 00E916]
B 0 to 4 5
Name Count value (HC0 to HC4)
Functions
After reset Indeterminate
RW R--
Count source (HC5)
0: HSYNC signal 1: Composite sync signal
0
RW
6, 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0."
0
R--
Fig. 8.10.12 Sync Pulse Counter Register
f(XIN)/213
Composite sync signal HSYNC signal
Reset 5-bit counter Counter
b5
Latch (5 bits)
Sync pulse counter register
Selection gate : connected to black side when reset.
Data bus
Fig. 8.10.13 Synchronous Signal Counter Block Diagram
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8.11 OSD FUNCTIONS
Table 8.11.1 outlines the OSD functions. This OSD function can display the following: the block display (32 characters 16 lines), the SPRITE display. And besides, the function can display the both display at the same time. There are 3 display modes and they are selected by a block unit. The display modes are selected by block control register i (i = 1 to 16). The features of each mode are described below.
Table.8.11.1 Features of Each Display Style
Display style Parameter Number of display characters Dot structure 16 20 dots (Character sidplay area: 16 26 dots) 510 kinds ROM 4 kinds 1, 2 1TC 1/2H, 1TC 1H 14 kinds 1, 2, 3 1TC 1/2H, 1TC 1H, 1.5TC 1/2H, 1.5TC 1H, 2TC 2H, 3TC 3H 62 kinds 1 kind RAM 8 kinds 1, 2 1TC 1/2H, 1TC 1H, 2TC 2H, 3TC 3H Block display CC mode (Closed caption mode) OSD mode (On-screem display mode) CDOSD mode (Color dot on-screen display mode) SPRITE display
32 characters 16 lines 16 20 dots 16 26 dots
1 character 16 20 dots
Kinds of characters Font memory Kinds of character sizes Pre-divide ratio (Note) Dot size
Attribute
Character font coloring
Smooth italic, Border under line, flash 1 screen: 8 kinds (per character unit) 1 screen: 15 kinds (per character unit) Max. 64 kinds Max. 64 kinds
1 screen: 8 kinds (per dot unit) 1 screen: 15 kinds (only specified dots are colored per character unit) Max. 64 kinds
1 screen: 8 kinds (per dot unit) Max. 64 kinds
Character background coloring Display layer OSD output Raster coloring Function Display expansion (multiline display)
Possible Possible (a character unit, 1 screen: 4 kinds, (a character unit,1 screen: 15 kinds, Max. 64 kinds) Max. 64 kinds) Layer 1 Layer 1 and layer 2 Layer 3 (with highest priority)
Analog R, G, B output (each 4 adjustment levels : 64 colors), Digital OUT1, OUT2 output Possible (a screen unit, max 64 kinds) Auto solid space function Triple layer OSD function, window function, blank funtion Possible
Notes1: The divide ratio of the frequency divider (the pre-divide circuit) is referred as "pre-divide ratio" hereafter. 2: The character size is specified with dot size and pre-divide ratio (refer to "2.11.3 Dot Size").
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The OSD circuit has an extended display mode. This mode allows multiple lines (16 lines or more) to be displayed on the screen by interrupting the display each time one line is displayed and rewriting data in the block for which display is terminated by software.
Figure 8.11.1 shows the configuration of OSD character display area. Figure 8.11.2 shows the block diagram of the OSD circuit. Figure 8.11.3 shows the OSD control register 1. Figure 8.11.4 shows the block control register i.
CC mode OSD mode
16 dots 16 dots Blank area
26 dots 20 dots
20 dots
Underline area Blank area : Displayed only in cc mode.
CDOSD mode
16 dots
Fig. 8.11.1 Configuration of OSD Character Display Area
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Clock for OSD OSC1 OSC2 HSYNC VSYNC
Control register for OSD Data slicer clock Display oscillation circuit (address 00CB16) (address 00CE16) (address 00CF16) (addresses 00D016 to 00DF16) (address 021516) (address 021616) (address 021716) (address 021816) (address 021916) (addresses 021C16, 021E16) (addresses 021D16, 021F16) (addresses 022016 to 023F16) (addresses 024116 to 024716, 024916 to 024F16) Left border control register 1, 2 (addresses 025016, 025116) Right border control register 1, 2 (addresses 025216, 025316) SPRITE vertical position registers 1, 2 (addresses 025416, 025516) SPRITE horizontal position registers 1, 2 (addresses 025616, 025716) SPRITE OSD control register (addresses 025816) OSD port control register OSD control register 1 Horizontal position register Block control register i OSD control register 2 Clock control register I/O polarity control register Raster color register OSD control register 3 Top border control register 1, 2 Bottom border control register 1, 2 Vertical position register 1i, 2i Color pallet register i
OSD control circuit
RAM for OSD (SPRITE) 16 dots 20 dots 3 planes
Shift register
OSD RAM 18 bits 32 characters 16 lines
OSD ROM (charater font) 16 dots 20 dots 510 characters
Shift register
Output circuit Shift register R OSD ROM (color dot font) 16 dots 26 dots 3 planes 62 characters G B OUT1 OUT2
Shift register Data bus
Fig. 8.11.2 Block Diagram of OSD Circuit
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OSD Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0 OSD control register 1 (OC1) [Address 00CE16] After reset Functions 0 : All-blocks display off 0 1 : All-blocks display on 0 : Normal scan mode 0 1 : Bi-scan mode 0 2 Border type selection 0 : All bordered 1 : Shadow bordered (See note 2) bit (OC12) 0 3 Flash mode selection 0 : Color signal of character background part does not flash bit (OC13) 1 : Color signal of character background part flashes B Name OSD control bit 0 (OC10) (See note 1) Scan mode selection 1 bit (OC11) 4 Automatic solid space control bit (OC14) 0 : OFF 1 : ON 0 0 RW RW RW RW RW
RW RW
5 Vertical window/blank 0 : OFF control bit (OC15) 1 : ON 6, 7 Layer mixing control bits (OC16, OC17) (See note 3)
b7 b6
0 0: Logic sum (OR) of layer 1's color and layer 2's color 0 1: Layer 1's color has priority 1 0: Layer 2's color has priority 1 1: Do not set.
0
RW
Notes 1 : Even this bit is switched during display, the display screen remains unchanged until a rising (falling) of the next VSYNC. 2 : Shadow border is output at right and bottom side of the font. 3 : OUT2 is always ORed, regardless of values of these bits.
Fig. 8.11.3 OSD Control Register 1
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Block Control Register i
b7 b6 b5 b4 b3 b2 b1 b0 Block control register i (BCi) (i=1 to 16) [Addresses 00D016 to 00DF16] B Name
b1 b0 Functions
Functions 0 0 1 1 0 1 0 1 Display OFF OSD mode CC mode CDOSD mode
After reset R W Indeterminate R W
0, 1 Display mode selection bits (BCi0, BCi1)
2 Border control bit 0 : Border OFF (BCi2) 1 : Border ON 3, 4 Dot size selection bits (BCi3, BCi4)
b6 b5 b4 0 0 1 1 0 0 1 1 0 0 0 0 1 1 b3 Pre-divide ratio 0 1 0 1 1 0 1 2 0 1 0 1 0 3 1 0 1 Dot size 1Tc 1/2H 1Tc 1H 2Tc 2H 3Tc 3H 1Tc 1/2H 1Tc 1H 2Tc 2H 3Tc 3H 1.5Tc 1/2H (See note 3) 1.5Tc 1H (See note 3) 1Tc 1/2H 1Tc 1H 2Tc 2H 3Tc 3H
Indeterminate R W Indeterminate R W
0
0
0
1
5, 6 Pre-divide ratio selection bit (BCi5, BCi6)
Indeterminate R W
1
1
1
1
7
Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is indeterminate.
Indeterminate R --
Notes 1: Tc : OSD clock cycle divided in pre-divide circuit 2: H : HSYNC 3: This character size is available only in Layer 2. At this time, set layer 1's pre-divide ratio = 2, layer 1's horizontal dot size = 1Tc.
Fig. 8.11.4 Block Control Register i (i = 1 to 16)
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8.11.1 Triple Layer OSD
Three built-in layers of display screens accommodate triple display of channels, volume, etc., closed caption, and sprite displays within layers 1 to 3. The layer to be displayed in each block is selected by bit 0 or 1 of the OSD control register 2 for each display mode (refer to Figure 8.11.7). Layer 3 always displays the sprite display.
When the layer 1 block and the layer 2 block overlay, the screen is composed (refer to Figure 8.11.5) with layer mixing by bit 6 or 7 of the OSD control register 1, as shown in Figure 8.11.3. Layer 3 always takes display priority of layers 1 and 2.
Notes 1: When mixing layer 1 and layer 2, note Table 8.11.2. 2: OUT2 is always ORed, regardless of values of bits 6, 7 of the OSD control register 1. And besides, even when OUT2 (layer 1 or layer 2) overlaps with SPRITE display (layer 3), OUT2 is output.
Table 8.11.2 Mixing Layer 1 and Layer 2 Block Parameter Display mode Pre-divide ratio Dot size Block in Layer 1 CC, OSD, CDOSD mode 1, 2 (CC mode) 1 to 3 (OSD, CDOSD mode) 1TC 1/2H, 1TC 1H (CC mode) 1TC 1H, 1TC 1/2H, 2TC 2H, 3TC 3H (OSD, CDOSD mode) Horizontal display start position Vertical display start position Arbitrary OSD, CDOSD mode Same as layer 1 Pre-divide ratio = 1 Pre-divide ratio = 2 1TC 1/2H 1TC 1/2H, 1.5TC 1/2H 1TC 1H 1TC 1H, 1.5TC 1H * Same saize as layer 1 * 1.5TC can be selected only when: layer 1's pre-divide ratio = 2 AND layer 1's horizontal dot size = 1TC. As this time, vertical dot size is the same as layer 1. Same position as layer 1 Block in Layer 2
Arbitrary However, when dot size is 2TC 2H or 2TC 3H, set difference between vertical display position of layer 1 and that of layer 2 as follows. *2TC 2H: 2H Units *3TC 3H: 3H Units
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Note : When layer 1 and SPRITE display overlay each other, only OUT2 in layer 1 is output. Block 9 Block 10 Sprite
...
A
Layer 1
SPRITE (except transparent)
A'
Layer 3
Block 15 Block 16 Layer 2
Block 1 Block 2
...
SPRITE
R, G, B of layer 1 OUT2 of layer 1
Block 7 Block 8 Layer 1
Fig. 8.11.5 Triple Layer OSD
Display example of layer 1 = "HELLO," layer 2 = "CH5"
CH5 HELLO
CH5 HELLO
CH5 HELLO
Logical sum (OR) of layer 1's color and layer 2's color (See note) Bit 7 = "0," bit 6 = "0"
Layer 1's color has priority Bit 7 = "0", bit 6 = "1"
Layer 2's color has priority Bit 7 = "1," bit 6 = "0"
Note: Layer mixing is not logical sum (OR) of colors, but that of each bit of color pallet register. Example) When logical sum (OR) is performed on color pallet 1 (00012) and color pallet 2 (00102), the color set to color pallet 3 (00112) is output, regardless of color pallets 1 and 2 contents.
Fig. 8.11.6 Display Example of Triple Layer OSD
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OSD Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0 OSD control register 2 (OC2) [Address 021516]
B
Name
Functions b1 b0 Layer 1 0 0 CC, OSD, CDOSD 0 1 CC, OSD 1 0 CC, CDOSD 1 1 CC Layer 2
At reset R W 0 RW
0, 1 Display layer selection bits (OC20, OC21)
2 3 4 5
CDOSD OSD CDOSD OSD (See note) R, G, B signal output 0: Digital output selection bit(OC22) 1: Analog output (4 gradations)
0 0 0 0
RW RW RW RW
Solid space output bit 0: OUT1 output (OC23) 1: OUT2 output Horizotal window/blank coutrol bit (OC24) Window/blank selection bit 1 (horizontal) (OC25) Window/blank selection bit 2 (vertical) (OC26) OSD interrupt request selection bit (OC27) 0: OFF 1: ON 0: Horizontal blank function 1: Horizontal window function 0: Vertical blank function 1: Vertical window function 0: At completion of layer 1 block display 1: At completion of layer 2 block display
6
0
RW
7
0
RW
Note: When setting bit 1 of the OSD port control register to "1," the value which is converted from the 4-adjustment-level analog to the 2-bit digital is output regardless of this bit value as follows : the high-order bit (R1, G1 and B1) is output from pins P52, P53 and P54, and the low-order bit is (R0, G0 and B0) output from pins P17, P15 and P16. And besides, when not using OSD function, the low-power dissipation can realize by setting this bit to "0."
Fig. 8.11.7 OSD Control Register 2
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8.11.2 Display Position
The display positions of characters are specified by a block. There are 16 blocks, blocks 1 to 16. Up to 32 characters can be displayed in each block (refer to "8.11.6 Memory for OSD"). The display position of each block can be set in both horizontal and vertical directions by software. The display position in the horizontal direction can be selected for all blocks in common from 256-step display positions in units of 4 TOSC (TOSC = OSD oscillation cycle). The display position in the vertical direction for each block can be selected from 1024-step display positions in units of 1 TH ( TH = HSYNC cycle). Blocks are displayed in conformance with the following rules: * When the display position is overlapped with another block (Figure 8.11.8 (b)), a lower block number (1 to 16) is displayed on the front. * When another block display position appears while one block is . displayed (Figure 8.11.8 (c)), the block with a larger set value as the vertical display start position is displayed. However, do not display block with the dot size of 2TC 2H or 3TC 3H during display period () of another block.
In the case of OSD mode block: 20 dots in vertical from the vertical display start position. In the case of CC or CDOSD mode block: 26 dots in vertical from the vertical display start position.
HP VP11, VP21 Block 1 VP12, VP22 Block 2 VP13, VP23 Block 3
(a) Example when each block is separated
HP VP11, VP21 = VP12, VP22 Block 1 (Block 2 is not displayed) (b) Example when block 2 overlaps with block 1
HP VP11, VP21 VP12, VP22 Block 1 Block 2 (c) Example when block 2 overlaps in process of block 1
Note: VP1i or VP2i (i : 1 to 16) indicates the vertical display start position of display block i.
Fig. 8.11.8 Display Position
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The display position in the vertical direction is determined by counting the horizontal sync signal (HSYNC). At this time, when VSYNC and HSYNC are positive polarity (negative polarity), it starts to count the rising edge (falling edge) of HSYNC signal from after fixed cycle of rising edge (falling edge) of VSYNC signal. So interval from rising edge (falling edge) of VSYNC signal to rising edge (falling edge) of HSYNC signal needs enough time (2 machine cycles or more) for avoiding jitter. The polarity of HSYNC and VSYNC signals can select with the I/O polarity control register (address 021716).
8 machine cycles or more
VSYNC signal input 0.25 to 0.50 [s] ( at f(XIN) = 8MHz) VSYNC control signal in microcomputer Period of counting HSYNC signal HSYNC signal input 8 machine cycles or more 1 2 3 4 5 (Note 2)
Not count When bits 0 and 1 of the I/O polarity control register (address 021716) are set to "1" (negative polarity) Notes 1 : The vertical position is determined by counting falling edge of HSYNC signal after rising edge of VSYNC control signal in the microcomputer. 2 : Do not generate falling edge of HSYNC signal near rising edge of VSYNC control signal in microcomputer to avoid jitter. 3 : The pulse width of VSYNC and HSYNC needs 8 machine cycles or more.
Fig. 8.11.9 Supplement Explanation for Display Position
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The vertical position for each block can be set in 1024 steps (where each step is 1TH (TH: HSYNC cycle)) as values "0016" to "FF16" in vertical position register 1i (i = 1 to 16) (addresses 022016 to 022F16) and values "0016" to "0316" in vertical position register 2i (i = 1 to 16) (addresses 023016 to 023F16). The vertical position registers are shown in Figures 8.11.10 and 8.11.11.
Vertical Position Register 1i
b7 b6 b5 b4 b3 b2 b1 b0 Vertical position register 1i (VP1i) (i = 1 to 16) [Addresses 022016 to 022F16] B Name 0 Control bits of vertical to display start positions 7 (VP1i0 to VP1i7) (See note 1) After reset R W Functions Vertical display start positions Indeterminate R W (low-order 8 bits) TH (setting value of low-order 2 bits of VP2i 162 + setting value of low-order 4 bits of VP1i 161 + setting value of low-order 4 bits of VP1i 160)
Notes 1: Do not "0016" and "0116" to VP1i at VP2i = "0016." 2: TH is cycle of HSYNC. 3: VP2i is vertical position register 2i.
Fig. 8.11.10 Vertical Position Register 1i (i = 1 to 16)
Vertical Position Register 2i
b7 b6 b5 b4 b3 b2 b1 b0 Vertical position register 2i (VP2i) (i = 1 to 16) [Addresses 023016 to 023F16] B Name 0, 1 Control bits of vertical display start positions (VP2i0, VP2i1) (See note 1) After reset R W Functions Vertical display start positions Indeterminate R W (high-order 2 bits) TH (setting value of low-order 2 bits of VP2i 162 + setting value of low-order 4 bits of VP1i 161 + setting value of low-order 4 bits of VP1i 160)
2 Nothing is assigned. These bits are write disable bits. Indeterminate R -- to When these bits are read out, the values are indeterminate. 7 Notes 1: Do not set "0016" and "0116" to VP1i at VP2i = "0016." 2: TH is cycle of HSYNC. 3: VP1i is vertical position register 1i.
Fig. 8.11.11 Vertical Position Register 2i (i = 1 to 16)
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The horizontal position is common to all blocks, and can be set in 256 steps (where 1 step is 4TOSC, TOSC being the oscillating cycle for display) as values "0016" to "FF16" in bits 0 to 7 of the horizontal position register (address 00CF16). The horizontal position register is shown in Figure 8.11.12.
Horizontal Position Register
b7 b6 b5 b4 b3 b2 b1 b0 Horizontal position register (HP) [Address 00CF16] After reset R W Name Functions Horizontal display start positions 0 Control bits of horizontal 0 RW 4TOSC to display start positions 1 (setting value of high-order 4 bits 16 (HP0 to HP7) 7 +setting value of low-order 4 bits 160 ) B Notes 1. The setting value synchronizes with the VSYNC. 2. TOSC = OSD oscillation period.
Fig. 8.11.12 Horizontal Position Register
Note : 1TC (TC : OSD clock cycle divided in pre-divide circuit) gap occurs between the horizontal display start position set by the horizontal position register and the most left dot of the 1st block. Accordingly, when 2 blocks have different pre-divide ratios, their horizontal display start position will not match. Ordinaly, this gap is 1TC regardless of character sizes, however, the gap is 1.5TC only when the character size is 1.5TC.
HSYNC 1TC Tdef 4TOSC N 1TC
Block 2 (Pre-divide ratio = 2) Block 1 (Pre-divide ratio = 1)
Note 1
1TC 1.5TC
N Tc Tosc Tdef
Block 3 (Pre-divide ratio = 3) Block 4 (Pre-divide ratio = 2, character size = 1.5Tc) : Value of horizontal position register (decimal notation) : OSD clock cycle divided in pre-divide circuit : OSD oscillation cycle : 50 Tosc
Fig. 8.11.13 Notes on Horizontal Display Start Position
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8.11.3 Dot Size
The dot size can be selected by a block unit. The dot size in vertical direction is determined by dividing HSYNC in the vertical dot size control circuit. The dot size in horizontal is determined by dividing the following clock in the horizontal dot size control circuit : the clock gained by dividing the OSD clock source (data slicer clock, OSC1, main clock) in the pre-divide circuit. The clock cycle divided in the pre-divide circuit is defined as 1TC. The dot size is specified by bits 6 to 3 of the block control register.
Refer to Figure 8.11.4 (the block control register i), refer to Figure 8.11.6 (the clock control register). The block diagram of dot size control circuit is shown in Figure 8.11.4.
Notes 1: The pre-divide ratio = 3 cannot be used in the CC mode. 2: The pre-divide ratio of the layer 2 must be same as that of the layer 1 by the block control register i. 3: In the bi-scan mode, the dot size in the vertical direction is 2 times as ompared with the normal mode. Refer to "8.11.13 Scan Mode" about the scan mode.
OSC1
Synchronous
circuit
Cycle 2 Cycle 3
Clock cycle = 1TC
Data slicer clock (See HSYNC note)
Horizontal dot size control circuit
Pre-divide circuit Vertical dot size control circuit OSD control circuit
Note: To use data slicer clock, set bit 0 of data slicer control register 1 to "1."
Fig. 8.11.14 Block Diagram of Dot Size Control Circuit
1 dot
1TC 1/2H 1H
1TC
2TC
3TC Scanning line of F1 (F2) Scanning line of F2 (F1) 3H
2H
In normal scan mode
Fig. 8.11.15 Definition of Dot Sizes
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8.11.4 Clock for OSD
As a clock for display to be used for OSD, it is possible to select one of the following 3 types. * Data slicer clock output from the data slicer (approximately 26 MHz) * Clock from the LC oscillator supplied from the pins OSC1 and OSC2 * Clock from the ceramic resonator or the quartz-crystal oscillator from the pins OSC1 and OSC2 The clock for display to be used for OSD can be selected by bit 7 of port P3 direction register, bit 2 and bit 1 of clock source control register (address 021616). If the pins OSC1 and OSC2 are not used as OSD clock input/output, these pins can be used as the sub-clock input/output, or port P6.
Table 8.11.3 Setting of P63/OSC1/XCIN, P64/OSC2/XCOUT Function Clock input/ Sub-clock output pins input/ Input port Registers for OSD output pins Bit 7 of Port P3 0 0 1 Direction Register Bit 2 1 1 0 0 Clock Control Register Bit 1 0 1 0 1
Clock Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0000
Clock control register (CS) [Address 021616]
B 0 1, 2
Name Clock selection bit (CS0)
Functions 0: Data slicer clock 1: OSC1 clock
After reset R W 0 0 RW RW
OSC1 oscillating mode b2 b1 selection bits (CS1, CS2) 0 0: 32kHz oscillating mode. 0 1: Used as input port of P63 and P64 (See note 1). 1 0: LC oscillating mode 1 1: Ceramic * quartz-crystal oscillating mode Fix these bits to "0." Test bit (See note 2)
3 to 6 7
0 0
RW RW
Note 1: Set bit 7 of address 00C716 to "1", when OSC1 and OSC2 are used as P63 and P64. 2: Be sure to set bit 7 to "0" for program of the mask and the EPROM versions. For the emulator MCU version (M37280ERSS), be sure to set bit 7 to "1" when using the data slicer clock for software debugging.
Fig. 8.11.16 Clock Control Register
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Data slicer circuit
"00"
(See note) Data slicer clock
32kHz OSC1 clock
"10"
"0"
OSD control circuit CS0
"1"
LC
Ceramic * quartz-crystal
CS2, CS1
"11"
Oscillating mode for OSD
Note : To use data slicer clock, set bit 0 of data slicer control register 1 to "1."
Fig. 8.11.17 Block Diagram of OSD Selection Circuit
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8.11.5 Field Determination Display
To display the block with vertical dot size of 1/2H, whether an even field or an odd field is determined through differences in a synchronizing signal waveform of interlacing system. The dot line 0 or 1 (refer to Figure 8.11.19) corresponding to the field is displayed alternately. In the following, the field determination standard for the case where both the horizontal sync signal and the vertical sync signal are negative-polarity inputs will be explained. A field determination is determined by detecting the time from a falling edge of the horizontal sync signal until a falling edge of the VSYNC control signal (refer to Figure
8.11.19) in the microcomputer and then comparing this time with the time of the previous field. When the time is longer than the comparing time, it is regarded as even field. When the time is shorter, it is regarded as odd field. The field determination flag changes at a rising edge of VSYNC control signal in the microcomputer. The contents of this field can be read out by the field determination flag (bit 7 of the I/O polarity control register at address 021716). A dot line is specified by bit 6 of the I/O polarity control register (refer to Figure 8.11.19). However, the field determination flag read out from the CPU is fixed to "0" at even field or "1" at odd field, regardless of bit 6.
I/O Polarity Control Register
b7 b6 b5 b4 b3 b2 b1 b0 I/O polarity control register (PC) [Address 021716]
B 0 1 2 3 4 5 6
Name HSYNC input polarity switch bit (PC0) VSYNC input polarity switch bit (PC1) R, G, B output polarity switch bit (PC2)
Functions 0 : Positive polarity input 1 : Negative polarity input 0 : Positive polarity input 1 : Negative polarity input 0 : Positive polarity output 1 : Negative polarity output
After reset R W 0 0 0 0 0 0 0 RW RW RW R-- RW RW RW
Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0". OUT1 output polarity 0 : Positive polarity output switch bit (PC4) 1 : Negative polarity output OUT2 output polarity switch bit (PC5) Display dot line selection bit (PC6) (See note) 0 : Positive polarity output 1 : Negative polarity output 0:" " 1:" " " at even field " at odd field " at even field " at odd field
7
Field determination flag(PC7)
0 : Even field 1 : Odd field
1
R--
Note: Refer to Fig. 12.11.19.
Fig. 8.11.18 I/O Polarity Control Register
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Both HSYNC signal and VSYNC signal are negative-polarity input Field Display dot line determination selection bit flag(Note)
HSYNC
Field
Display dot line
VSYNC and VSYNC control signal in microcomputer Upper : VSYNC signal Lower : VSYNC control signal in microcomputer
(n-1) field (Odd-numbered) T1
Odd
0.25 to 0.50[s] at f(XIN) =8 MHz
0 (n) field (Even-numbered) T2 Even 0 (T2 > T1) 1
Dot line 1 Dot line 0
0 (n+1) field (Odd-numbered) T3 Odd 1 (T3 < T2) 1
Dot line 0
Dot line 1
When using the field determination flag, be sure to set bit 0 of the PWM mode register 1 (address 020A16) to "0." 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 CC mode * CDOSD mode 2 34 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 OSDS mode When the display dot line selection bit is "0," the " " font is displayed at even field, the " " font is displayed at odd field. Bit 7 of the I/O polarity control register can be read as the field determination flag : "1" is read at odd field, "0" is read at even field. 12 34 5 6 7 8 9 10 11 12 13 14 15 16
OSD ROM font configuration diagram
Note : The field determination flag changes at a rising edge of the VSYNC control signal (negative-polarity input) in the microcomputer.
Fig. 8.11.19 Relation Between Field Determination Flag and Display Font
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8.11.6 Memory for OSD
There are 2 types of memory for OSD : OSD ROM (addresses 1080016 to 157FF16 and 1800016 to 1ACFF16) used to specify character dot data and OSD RAM (addresses 070016 to 07A716 and 080016 to 0FDF16) used to specify the kinds of display characters, display colors, and SPRITE display. The following describes each type of memory.
(1) OSD ROM (addresses 1080016 to 157FF16, 1800016 to 1ACFF16) The dot pattern data for OSD characters is stored in the character font area in the OSD ROM and the CD font data for OSD characters is stored in the color dot font area in the OSD ROM. To specify the kinds of the character font and the CD font, it is necessary to write the character code into the OSD RAM. The modes are selected by bit 3 of the OSD control register 3 for each screen. The character font data storing address is shown in Figure 8.11.20. The CD font data storing address is shown in Figure 8.11.21. The 510 kinds of character font and 62 kinds of CD font can be stored.
OSD ROM address of character font data
OSD ROM address bit Line number / Character code / Area bit AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
Area bit
1
0
Line number
Character code
Line number = "0216" to "1516" Character code = "0016" to "1FF16" ("0FF16" and "10016" can not be used. Write "FF16" to corresponding addresses.) Area bit = 0: Left area 1: Right area For example : The font data of the hatching area of the character code AA16 is 1 0010 1001 0101 0100 2 =1295416
Line number 0216 0316 0416 0516 0616 0716 0816 0916 0A16 0B16 0C16 0D16 0E16 0F16 1016 1116 1216 1316 1416 1516
b7
Left area
b0 b7
Right area
b0
Character code AA16
Fig. 8.11.20 Character Font Data Storing Address
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OSD ROM address of CD font data
OSD ROM address bit
Line number/CD code/ Area bit
AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Area bit
1
1
0
Plain selection bit
Line number
CD code
Line number = "0016" to "1916" = "0016" to "3F16" ("1F16" and "2016" cannot be used. Write "FF16" to the corresponding address.) CD code = 0 : Left area 1 : Right area Area bit Example) "0316" is stored to address 1A77516 (Plain 2), "C016" is stored to address 1977516 (Plain 1), and "F816" is stored to address 1877516 (Plain 0) as the font data of the hatching area of the CD code 3A16.
Plain 2
(Color pallet selection bit 2)
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 "0316" 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Plain 1
(Color pallet selection bit 1)
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
Plain 0
(Color pallet selection bit 0)
00 00 00 00 00 00 00 00 00 00 00 11 11 11 11 00 00 00 00 00 00 00 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 00 00 00 00 00 00 00 00 00 00 00 11 11 11 11 00 00 00 00 00 00 00 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 "F816" 0 0 0 0 0 0 0 0 0 0 0
0 "C016" 0
Line number b7 0016 0116 0216 0316 0416 0516 0616 0716 0816 0916 0A16 0B16 0C16 0D16 0E16 0F16 1016 1116 1216 1316 1416 1516 1616 1716 1816 1916
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
Left area
4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 4 4 4 0 0 0 0 0 0 0 0 0 2 2 2 2 0 0 0 0 0 0 0 0 0 4 4 4 4 0 0 0 0 0 0 0 0 0 2 2 2 2 0 0 0 0 0 0 0 0 0 4 4 4 4 0 0 0 0 0 0 0 0 0 2 2 2 2 0 0 0 0 0 0 0 0 0 4 4 4 4 0 0 1 1 1 1 1 1 1 3 3 3 3 1 1 1 1 1 1 1 0 0 4 4
b0 b7 4 4 0 0 1 1 1 1 1 1 1 3 3 3 3 1 1 1 1 1 1 1 0 0 4 4 4 4 0 0 1 1 1 1 1 1 1 3 3 3 3 1 1 1 1 1 1 1 0 0 4 4 4 4 0 0 1 1 1 1 1 1 1 3 3 3 3 1 1 1 1 1 1 1 0 0 4 4
Right area
4 4 0 0 0 0 0 0 0 0 0 2 2 2 2 0 0 0 0 0 0 0 0 0 4 4 4 4 0 0 0 0 0 0 0 0 0 2 2 2 2 0 0 0 0 0 0 0 0 0 4 4 4 4 0 0 0 0 0 0 0 0 0 2 2 2 2 0 0 0 0 0 0 0 0 0 4 4 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
b0 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
Line number b7 0016 0116 0216 0316 0416 0516 0616 0716 0816 0916 0A16 0B16 0C16 0D16 0E16 0F16 1016 1116 1216 1316 1416 1516 1616 1716 1816 1916
Left area
b0 b7
Right area
b0
When bit 3 of OSD control register 3 is "0 (1)"
0 Color pallet set by RC13 to
RC16 of OSD RAM is selected
1 Color pallet 1 (9) is selected 2 Color pallet 2 (10) is selected 3 Color pallet 3 (11) is selected 4 Color pallet 4 (12) is selected
CD code 3A16
Display example
Fig. 8.11.21 Color Dot Font Data Storing Address
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(2) OSD RAM (addresses 070016 to 07A716, 080016 to 0FFF16) The OSD RAM for SPRITE consisting of 3 planes, is assigned to addresses 070016 to 07A716. Each plane corresponds to each color pallet selection bit and the color pallet of each dot is determined from among 8 kinds. The OSD RAM for character is allocated at addresses 080016 to 0FFF16, and is divided into a display character code specification part, color code 1 specification part, and color code 2 specification part for each block. Tables 8.11.5 and 8.11.6 show the contents of the OSD RAM. For example, to display 1 character position (the left edge) in block 1, write the character code in address 080016, write color code 1 at 082016, and write color code 2 at 084016. The structure of the OSD RAM is shown in Figure 8.11.23.
Note : For the layer 2 's OSD mode block with dot size of 1.5TC 1/2H and 1.5TC 1H, the 3nth (n = 1 to 10) character is skipped as compared with ordinary block (blocks with dot size of 1TC 1/2H, or blocks on the layer 1). Accordingly, maximum 22 characters are only displayed in 1 block. Blocks with dot size of 1TC 1/2H and 1TC 1H, or blocks on the layer 1 However, note the following: * In OSD mode The character is not displayed, and only the left 1/3 part of the 22nd character back ground is displayed in the 22nd's character area. When not displaying this background, set transparent for background. * In CDOSD mode The character is not displayed, and color pallet color specified by bit 3 to 6 of color code 1 can be output in the 22nd's character area (left 1/3 part). The RAM data for the 3nth character does not effect the display. Any character data can be stored here (refer to Figure 8.11.22).
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Table 8.11.4 Contents of OSD RAM (SPRITE) Line (from top) Dot (from left) Line 1 Line 2 : Line 19 Line 20 Dots 1 to 8 Dots 9 to 16 Dots 1 to 8 Dots 9 to 16 : Dots 1 to 8 Dots 9 to 16 Dots 1 to 8 Dots 9 to 16
Plain 0 Plain 1 (Color pallet selection bit 0) (Color pallet selection bit 1) 070016 074016 070116 074116 070216 074216 070316 074316 : 072416 072516 072616 072716 : 076416 076516 076616 076716
Plain 2 (Color pallet selection bit 2) 078016 078116 078216 078316 : 07A416 07A516 07A616 07A716
Plain 2
b7 b0 b7 b0 b7
Plain 1
b0 b7 b0 b7
Plain 0
b0 b7 b0
780 782
781 783
Line 1 Line 2
740 742
741 743
Line 1 Line 2
700 702
701 703
Line 1 Line 2
7A4 7A6
7A5 7A7
Line 19 Line 20
764 766
765 767
Line 19 Line 20
724 726
725 727
Line 19 Line 20
Dot number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Line number
Display sequence RAM address order
1 1
2 2
3 4
4 5
5 7
6 8
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22
* 1.5Tc size block
10 11 13 14 16 17 19 20 22 23 25 26 28 29 31 32
Display sequence 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RAM address 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 order
* 1Tc size block
Fig. 8.11.22 RAM Data for 3nth Character
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Table 8.11.5 Contents of OSD RAM (Character) Block Display Position (from left) Character Code Specification 1st character 080016 2nd character 080116 Block 1 : : 31st character 081E16 32nd character 081F16 1st character 088016 2nd character 088116 Block 2 : : 31st character 089E16 32nd character 089F16 1st character 090016 2nd character 090116 Block 3 : : 31st character 091E16 32nd character 091F16 1st character 098016 2nd character 098116 : Block 4 : 099E16 31st character 099F16 32nd character 0A0016 1st character 0A0116 2nd character : Block 5 : 0A1E16 31st character 0A1F16 32nd character 0A8016 1st character 2nd character 0A8116 Block 6 : : 31st character 0A9E16 32nd character 0A9F16 1st character 0B0016 2nd character 0B0116 Block 7 : : 31st character 0B1E16 32nd character 0B1F16 1st character 0B8016 2nd character 0B8116 Block 8 : : 31st character 0B9E16 32nd character 0B9F16 1st character 0C0016 2nd character 0C0116 Block 9 : : 31st character 0C1E16 32nd character 0C1F16 1st character 0C8016 2nd character 0C8116 Block 10 : : 31st character 0C9E16 32nd character 0C9F16
Color Code 1 Specification 082016 082116 : 083E16 083F16 08A016 08A116 : 08BE16 08BF16 092016 092116 : 093E16 093F16 09A016 09A116 : 09BE16 09BF16 0A2016 0A2116 : 0A3E16 0A3F16 0AA016 0AA116 : 0ABE16 0ABF16 0B2016 0B2116 : 0B3E16 0B3F16 0BA016 0BA116 : 0BBE16 0BBF16 0C2016 0C2116 : 0C3E16 0C3F16 0CA016 0CA116 : 0CBE16 0CBF16
Color Code 2 Specification 084016 084116 : 085E16 085F16 08C016 08C116 : 08DE16 08DF16 094016 094116 : 095E16 095F16 09C016 09C116 : 09DE16 09DF16 0A4016 0A4116 : 0A5E16 0A5F16 0AC016 0AC116 : 0ADE16 0ADF16 0B4016 0B4116 : 0B5E16 0B5F16 0BC016 0BC116 : 0BDE16 0BDF16 0C4016 0C4116 : 0C5E16 0C5F16 0CC016 0CC116 : 0CDE16 0CDF16
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Table 8.11.6 Contents of OSD RAM (continued) Block Display Position (from left) Character Code Specification 1st character 0D0016 2nd character 0D0116 Block 11 : : 31st character 0D1E16 32nd character 0D1F16 1st character 0D8016 2nd character 0D8116 Block 12 : : 31st character 0D9E16 32nd character 0D9F16 1st character 0E0016 2nd character 0E0116 Block 13 : : 31st character 0E1E16 32nd character 0E1F16 1st character 0E8016 2nd character 0E8116 : Block 14 : 0E9E16 31st character 0E9F16 32nd character 0F0016 1st character 0F0116 2nd character : Block 15 : 0F1E16 31st character 0F1F16 32nd character 0F8016 1st character 2nd character 0F8116 Block 16 : : 31st character 0F9E16 32nd character 0F9F16
Color Code 1 Specification 0D2016 0D2116 : 0D3E16 0D3F16 0DA016 0DA116 : 0DBE16 0DBF16 0E2016 0E2116 : 0E3E16 0E3F16 0EA016 0EA116 : 0EBE16 0EBF16 0F2016 0F2116 : 0F3E16 0F3F16 0FA016 0FA116 : 0FBE16 0FBF16
Color Code 2Specification 0D4016 0D4116 : 0D5E16 0D5F16 0DC016 0DC116 : 0DDE16 0DDF16 0E4016 0E4116 : 0E5E16 0E5F16 0EC016 0EC116 : 0EDE16 0EDF16 0F4016 0F4116 : 0F5E16 0F5F16 0FC016 0FC116 : 0FDE16 0FDF16
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Note: Do not read from/write to the addresses in Table 8.11.7.
Table 8.11.7 List of Access Disable Addresses
0 8 6 0 16 0 8 E 0 10 0 9 6 0 16 0 9 E 0 16 0 A 6 0 16 0 A E 0 16 0 B 6 0 16 0 B E 0 16
to to to to to to to to
0 8 7 F 16 0 8 F F16 0 9 7 F 16 0 9 F F16 0 A 7 F 16 0 A F F16 0 B 7 F 16 0 B F F16
0 C 6 0 16 0 C E 0 16 0 D 6 0 16 0 D E 0 16 0 E 6 0 16 0 E E 0 16 0 F 6 0 16 0 F E 016
to to to to to to to to
0 C 7 F 16 0 C F F16 0 D 7 F 16 0 D F F16 0 E 7 F 16 0 E F F16 0 F 7 F16 0 F F F16
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Blocks 1 to 16 b7 RF7 b0 b7 b0 b1 b0
RF6 RF5 RF4 RF3 RF2 RF1 RF0 RC17 RC16 RC15 RC14 RC13 RC12 RC11 RC10 RC21 RC20
Character code
Color code 1
Color code 2
CC mode Bit RF0 RF1 RF2 RF3 RF4 RF5 RF6 RF7 RC10 RC11 Charactercode (High-order1bits) Color pallet selection bit 0 Specify color pallet for character (See note 5) Bit name Character code (Low-order 8 bits) Function Specify character code in OSD ROM (See note 3) Bit name Character code (Loworder 8 bits)
OSD mode Function Specify character code in OSD ROM (See note 3) CD code (6 bits)
CDOSD mode Bit name Function Specify character code in OSD ROM (color dot) (See note 4)
Charactercode (High-order1bits) Color pallet selection bit Color pallet selection bit Color pallet selection bit Color pallet selection bit 3 Specify color pallet for character (See note 5)
Not used
Character Characterbackground
RC12 RC13 RC14 RC15 RC16
Color pallet selection bit 1 Color pallet selection bit 2 0: Italic OFF 1: Italic ON
Character
Color pallet selection bit 0 Color pallet selection bit 1 Color pallet selection bit 2 Color pallet selection bit 3 Specify a dot which selects color pallet 0 or 8 by OSD ROM (See note 6)
Italic control Flash control Underline control
Dot color
Characterbackground
0: Flash OFF 1: Flash ON 0: Underline OFF 1: Underline ON
Color pallet selection bit 0 Color pallet selection bit 1
Specify color pallet for background (See note 5)
RC17 RC20 RC21
OUT2 output control Color pallet selection bit 0 Color pallet selection bit 1
0:OUT2outputOFF 1:OUT2outputON Specify color pallet for background (See note 5)
OUT2 output control
0:OUT2outputOFF 1:OUT2outputON
OUT2 output control
0:OUT2outputOFF 1:OUT2outputON
Color pallet Specify color pallet selection bit 2 for background (See note 5) Color pallet selection bit 3
Notes 1: Read value of bits 2 to 7 of the color code 2 is undefined. 2: For "not used" bits, the write value is read. 3: Do not use character code "0FF16," "10016." 4: Do not use character code "1F16," "2016." 5: Refer to Figure 8.11.24. 6: Only CDOSD mode, a dot which selects color pallet 0 or 8 is colored to the color pallet set by RC13 to RC16 of OSD RAM in character units. Fig. 8.11.23 Structure of OSD RAM
Characterbackground
Not used
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8.11.7 Character Color
As shown in Figure 8.11.24, there are 16 built-in color pallets. Color pallet 0 is fixed at transparent, and color pallet 8 is fixed at black. The remaining 14 colors can be set to any of the 64 colors available. The setting procedure for character colors is as follows: * CC mode ................................. 8 kinds Color pallet selection range (color pallets 0 to 7 or 8 to 15) can be selected by bit 0 of the OSD control register 3 (address 021916). Color pallets are set by bits RC11 to RC13 of the OSD RAM from among the selection range. * OSD mode .............................. 15 kinds Color pallets are set by bits RC11 to RC14 of the OSD RAM. * CDOSD mode ......................... 8 kinds Color pallet selection range (color pallets 0 to 7 or 8 to 15) can be selected by bit 3 of the OSD control register 3 (address 021916). Color pallets are set in dot units according to the CD font data (the OSD RAM contents)from among the selection range. Only in CDOSD mode, a dot which selects color pallet 0 or 8 is colored to the color pallet set by RC13 to RC16 of OSD RAM in character units. * SPRITE display ....................... 8 kinds Color pallet selection range (color pallets 0 to 7 or 8 to 15) can be selected by bit 4 of the OSD control register 3 (address 021916). Color pallets are set in dot units according to the CD font data (the OSD RAM contents) from among the selection range.
Notes 1: Color pallet 8 is always selected for bordering and solid space output (OUT 1 output) regardless of the set value in the register. 2: Color pallet 0 (transparent) and the transparent setting of other color pallets will differ. When there are multiple layers overlapping (on top of each other, piled up), and the priority layer is color pallet 0 (transparent), the bottom layer is displayed, but if the priority layer is the transparent setting of any other color pallet, the background is displayed without displaying the bottom layer (refer to Figure 8.11.26).
8.11.8 Character Background Color
The display area around the characters can be colored in with a character background color. Character background colors are set in character units. * CC mode ................................. 4 kinds Color pallet selection range (color pallets 0 to 3, 4 to 7, 8 to 11, or 12 to 15) can be selected by bits 1 and 2 of the OSD control register 3 (address 021916). Color pallets are set by bits RC20 and RC21 of the OSD RAM from among the selection range. * OSD mode .............................. 15 kinds Color pallets are set by bits RC15, RC16, RC20, and RC21 of the OSD RAM.
Note : The character background is displayed in the following part: (character display area) - (character font) - (border). Accordingly, the character background color and the color signal for these two sections cannot be mixed.
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(See note 1) CC mode (background) Color pallet 0 (Transparent) Color pallet 1 Color pallet 2 Color pallet 3 Color pallet 4 Color pallet 5 Color pallet 6 Color pallet 7 Color pallet 8 (Black) Color pallet 9 Color pallet 10 Color pallet 11 Color pallet 12 Color pallet 13 Color pallet 14 Color pallet 15 Select one color pallet in screen units.
(See note 1)
CC mode (character) SPRITE display CDOSD mode (character) (See note 2)
OSD mode (character, background)
Select either color pallet in screen units.
Any color pallet can be selected.
Notes 1: Color pallets are selected by OSD control register 3 (address 021916). 2: Only in CDOSD mode, a dot which selects color pallet 0 or 8 is colored to of OSD RAM in character units.
Fig. 8.11.24 Color Code Selection
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Dot area specified to color pallet 1
Set values of OSD RAM (RC16 to RC13) 0000 0001 0010 Transparent Black Blue
Dot area specified to color pallet 0
When setting black and blue to color pallets 1 and 2, respectively (only in CDOSD mode).
Fig. 8.11.25 Set of Color Pallet 0 or 8 in CDROM Mode
Color pallet 1 (Transparent) Color pallet 0 (Transparent) Layer 1 (CC mode)
26 dots
Black Blue
26 dots 20 dots
Color pallet 2 (Blue)
Transparent (video signal)
20 dots
Layer 2 (OSD mode)
When layer 1 has priority. Color pallet 8 (Black)
Fig. 8.11.26 Difference Between Color Code 0 (Transparent) and Transparent Setting of Other Color Codes
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OSD Control Register 3
b7 b6 b5 b4 b3 b2 b1 b0 OSD control register 3 (OC3) [Address 021916]
B 0
Name CC mode character color selection bit (OC30)
Functions 0: Color code 0 to 7 1: Color code 8 to 15
b1 b1
After reset R W 0 0 RW RW
1, 2 CC mode character background color selection bits (OC31, OC32) (See note) 3 4 5 6 7 CDOSD mode character color selection bit (OC33) SPRITE color selection bit (OC34) OSD mode window control bit (OC35) CC mode window control bit (OC36) CDOSD mode window control bit (OC37)
0 0 1 1
0: Color code 0 to 3 1: Color code 4 to 7 0: Color code 8 to 11 1: Color code 12 to 15
0: Color code 0 to 7 1: Color code 8 to 15 0: Color code 0 to 7 1: Color code 8 to 15 0: Window OFF 1: Window ON 0: Window OFF 1: Window ON 0: Window OFF 1: Window ON
0 0 0 0 0
RW RW RW RW RW
Note: Color pallet 8 is always selected for solid space (when OUT1 output is selected), regardress of value of this register.
Fig. 8.11.27 OSD Control Register 3
Color Pallet Register i
b7 b6 b5 b4 b3 b2 b1 b0 Color pallet register i (CRi) (i = 1 to 7, 9 to15) [Addresses 024116 to 024716, 024916 to 024F16]
B
Name
b0 b1
Functions 0 0 1 1 0 0 1 1 0 0 1 1 0: No output (See note) 1: 1/3 V CC 0: 2/3 V CC 1: V CC 0: No output (See note) 1: 1/3 V CC 0: 2/3 V CC 1: V CC 0: No output (See note) 1: 1/3 V CC 0: 2/3 V CC 1: V CC
Afterreset R W Indeterminate R W
0, 1 R signal output control bits (CRi0, CRi1)
2, 3 G signal output control bits (CRi2, CRi3)
b3 b2
Indeterminate R W
4, 5 B signal output control bits (CRi4, CRi5)
b5 b4
Indeterminate R W
6 7
OUT1 signal output control bit (CRi6)
0: No output 1: Output
Indeterminate R W Indeterminate R --
Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is indeterminate.
Note: When selecting digital output, the output is VCC at all values other than "00."
Fig. 8.11.28 Color Pallet Register i (i = 1 to 7, 9 to 15)
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8.11.9 OUT1, OUT2 Signals
The OUT1, OUT2 signals are used to control the luminance of the video signal. The output waveform of the OUT1, OUT2 signals is controlled by bit 6 of the color code register i (refer to Figure 8.11.28),
bits 2 and 7 of the block control register i (refer to Figure 8.11.4) and RC17 of OSD RAM. The setting values for controlling OUT1, OUT2 and the corresponding output waveform is shown in Figure 8.11.29
Conditions OUT2 output control (RC 17 of OSD RAM)
Border output control bit (See note) (Bit 2 of block control register i) OUT1 control bit (See note) (b6 of color pallet register i)
Output waveform
Background
Character
0 0 1 0 0 1 1 OUT1 signal 0 0 1 1 0 1 1
H L
H L H L H L H L H L H L H L H L
0 OUT2 signal 1

H L
Notes 1: This control is only valid in the OSD mode. It is invalid in CC/CDOSD mode . 2: In the CDOSD mode, coloring is performed for each dot. Accordingly, OUT1 outputs to dots which bit 6 of the color pallet register i is set to "0." 3: OUT2 cannot be output in sprite OSD. 4: is an arbitrary value.
Fig. 8.11.29 Setting Value for Controlling OUT1, OUT2 and Corresponding Output Waveform
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8.11.10 Attribute
The attributes (flash, underline, italic) are controlled to the character font. The attributes to be controlled are different depending on each mode. CC mode .................... Flash, underline, italic for each character OSD mode ................. Border (all bordered, shadow bordered can be selected) for each block (1) Under line The underline is output at the 23rd and 24th lines in vertical direction only in the CC mode. The underline is controlled by RC16 of OSD RAM. The color of underline is the same color as that of the character font. (2) Flash The parts of the character font, the underline, and the character background are flashed only in the CC mode. The flash for each character is controlled by RC15 of OSD RAM. The ON/OFF for flash is controlled by bit 3 of the OSD control register 1 (refer to Figure 8.11.3). When this bit is "0", only character font and underline flash. When "1", for a character without solid space output, R, G, B and OUT1 (all display area) flash, for a character with solid space output, only R, G and B (all display area) flash. The flash cycle bases on the VSYNC count. * VSYNC cycle 48 800 ms (at flash ON) * VSYNC cycle 16 267 ms (at flash OFF) (3) Italic The italic is made by slanting the font stored in OSD ROM to the right only in the CC mode. The italic is controlled by RC14 of OSD RAM. The display example of attribute is shown in Figure 8.11.31. In this case, "R" is displayed.
Notes 1: When setting both the italic and the flash, the italic character flashes. 2: When a flash character (with flash character background) ajoin on the right side of a non-flash italic character, parts out of the non-flash italic character is also flashed. 3: OUT2 is not flashed. 4: When the pre-divide ratio = 1, the italic character with slant of 1 dot 5 steps is displayed (refer to Figure 8.11.30 (c)). When the pre-divide ratio = 2, the italic character with slant of 1/2 dot 10 steps is displayed (refer to Figure 8.11.30 (d)). 5: The boundary of character color is displayed in italic. However, the boundary of character background color is not affected by the italic (refer to Figure 8.11.31). 6: The adjacent character (one side or both side) to an italic character is displayed in italic even when the character is not specified to display in italic (refer to Figure 8.11.31). 7: When displaying the 32nd character in the italic and when solid space is off (OC14 = "0"), parts out of character area is not displayed. 8: When displaying the italic character in the block with the pre-divide ratio = 1, set the OSD clock frequency to 11 MHz to 14 MHz.
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Color code 1
Color code 1
Bit 6
Bit 4
Bit 6
Bit 4
0
0
1
0
(a) Ordinary
(b) Underline
Color code 1
Color code 1
Bit 6
Bit 4
Bit 6
Bit 4
0
1
1
1
(c) Italic
(d) Under line and Italic
Color code Bit 4 Bit 5 Bit 6 (RC 16) (RC 15) (RC 16) flash flash flash
1
1
1
ON OFF OFF (e) Under line and Italic and flash
ON
Fig. 8.11.30 Example of Attribute Display (in CC Mode)
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26th chracter (Refer to "12.11.10 Note 6") (Refer to "12.11.10 Note 6")
32nd chracter
Bit 4 of color code 1
1
0
0
1
1
0
1
Notes 1 : The dotted line is the boundary of character color. 2 : When bit 4 of OSD control register 1 is "0."
Fig. 8.11.31 Example of Italic Display
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(4) Border The border is output only in the OSD mode. The all bordered (bordering around of character font) and the shadow bordered (bordering right and bottom sides of character font) are selected (refer to Figure 8.11.31) by bit 2 of the OSD control register 1 (refer to Figure 8.11.3). The ON/OFF switch for borders can be controlled in block units by bit 2 of the block control register i (refer to Figure 8.11.4). The OUT1 signal is used for border output. The border color is fixed at color code 8 (block). The border color for each screen is specified by the border color register i.
The horizontal size (x) of border is 1TC (OSD clock cycle divided in the pre-divide circuit) regardless of the character font dot size. However, only when the pre-divide ratio = 2 and character size = 1.5TC, the horizontal size is 1.5TC. The vertical size (y) different depending on the screen scan mode and the vertical dot size of character font.
Notes 1: T h e b o r d e r d o t a r e a i s t h e s h a d e d a r e a a s s h o w n i n Figure 8.11.34. 2: When the border dot overlaps on the next character font, the character font has priority (refer to Figure 8.11.35 A). When the border dot overlaps on the next character back ground, the border has priority (refer to Figure 8.11.35 B). 3: The border in vertical out of character area is not displayed (refer to Figure 8.11.35).
All bordered
Fig. 8.11.32 Example of Border Display
Shadow bordered
y x
Scan mode Border dot size Vertical dot size of character font Horizontal size (x) Vertical size (y) Normal scan mode Bi-scan mode
1/2H
1H, 2H, 3H
1/2H, 1H, 2H, 3H
1TC (OSD clock cycle divided in pre-divide circuit) 1.5TC when selecting 1.5TC for character size.
1/2H
1H
1H
Fig. 8.11.33 Horizontal and Vertical Size of Border
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OSD mode
16 dots
Character font area
1 dot width of border
20 dots
1 dot width of border
Fig. 8.11.34 Border Area
Character boundary B
Character boundary A
Character boundary B
Fig. 8.11.35 Border Priority
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8.11.11 Multiline Display
This microcomputer can ordinarily display 16 lines on the CRT screen by displaying 16 blocks at different vertical positions. In addition, it can display up to 16 lines by using OSD interrupts. An OSD interrupt request occurs at the point at which display of each block has been completed. In other words, when a scanning line reaches the point of the display position (specified by the vertical position registers) of a certain block, the character display of that block starts, and an interrupt occurs at the point at which the scanning line exceeds the block. The mode in which an OSD interrupt occurs is different depending on the setting of the OSD control register 2 (refer to Figure 8.11.7). * When bit 7 of the OSD control register 2 is "0" An OSD interrupt request occurs at the completion of layer 1 block display. * When bit 7 of the OSD control register 2 is "1" An OSD interrupt request occurs at the completion of layer 2 block display.
Notes 1: An OSD interrupt does not occur at the end of display when the block is not displayed. In other words, if a block is set to off display by the display control bit of the block control register i (addresses 00D016 to 00DF16), an OSD interrupt request does not occur (refer to Figure 8.11.36 (A)). 2: When another block display appeares while one block is displayed, an OSD interrupt request occurs only once at the end of the another block display (refer to Figure 8.11.36 (B)). 3: On the screen setting window, an OSD interrupt occurs even at the end of the CC mode block (off display) out of window (refer to Figure 8.11.36 (C)).
Block 1 (on display) Block 2 (on display) Block 3 (on display) Block 4 (on display)
"OSD interrupt request" "OSD interrupt request" "OSD interrupt request" "OSD interrupt request"
Block 1 (on display) Block 2 (on display) Block 3 (off display) Block 4 (off display)
"OSD interrupt request" "OSD interrupt request" No "OSD interrupt request" No "OSD interrupt request"
On display (OSD interrupt request occurs at the end of block display) (A)
Off display (OSD interrupt request does not occur at the end of block display)
Block 1 "OSD interrupt request" Block 1 Block 2
No "OSD interrupt request" "OSD interrupt request"
Block 2 "OSD interrupt request" Block 3 "OSD interrupt request"
Window
(B)
(C)
Fig. 8.11.36 Note on Occurence of OSD Interrupt
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8.11.12 Automatic Solid Space Function
This function generates automatically the solid space (OUT1 or OUT2 blank output) of the character area in the CC mode. The solid space is output in the following area : * Any character area except character code "00916 " * Character area on the left and right sides of the above character This function is turned on and off by bit 4 of the OSD control register 1 (refer to Figure 8.11.3). And the OUT1 output or OUT2 output can be selected by bit 3 of OSD control register 2.
Note: When selecting OUT1 as solid space output, character background color with solid space output is fixed to color pallet 8 (black) regardless of setting.
Table 8.11.7 Setting for Automatic Solid Space 0 Bit 4 of OSD Control Register 1 Bit 3 of OSD Control Register 2 0 1 RC17 of OSD RAM 0 1 0 1 OUT1 Output Signal *Character font area *Character font area *Character background area *Character background area OFF *Character OFF *Character OUT2 Output Signal display area display area 1 0 0 1 *Solid space area OFF *Character display area 1 0 1 *Character font area *Character background area OFF *Solid space *Character display area
When setting the character code "00516" as the character A, "00616" as the character B.
(OSD RAM)
00516 00916 00916 00916 00616 00616 * * * 00616
(Display screen)
***
1st 2nd character character
No blank output
32nd character
Fig. 8.11.37 Display Screen Example of Automatic Solid Space
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8.11.13 Scan Mode
This microcomputer has the bi-scan mode for corresponding to HSYNC of double speed frequency. In the bi-scan mode, the vertical start display position and the vertical size is two times as compared with the normal scan mode. The scan mode is selected by bit 1 of the OSD control register 1 (refer to Figure 8.11.3). Table 8.11.8 Setting for Scan Mode Scan Mode Normal Scan Parameter Bit 1 of OSD Control Register 1 Vertical Display Start Position Vertical Dot Size 0 Value of vertical position register 1H 1TC 1/2H 1TC 1H 2TC 2H 3TC 3H Bi-Scan 1 Value of vertical position register 2H 1TC 1H 1TC 2H 2TC 4H 3TC 6H
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8.11.14 Window Function
The window function can be set windows on-screen, and output OSD within only the area where the window is set. The ON/OFF for vertical window function is performed by bit 5 of OSD control register 1 and is used to select vertical window function or vertical blank function by bit 6 of OSD control register 2. Accordingly, the vertical window function cannot be used simultaneously with the vertical blank function. The display mode to validate the window function is selected by bits 5 to 7 of OSD control register 3. The top boundary is set by top border control registers 1 and 2 (TB1, TB2) and the bottom boundary is set by bottom border control registers 1 and 2 (BB1, BB2). The ON/OFF for horizontal window function is performed by bit 4 of OSD control register 2 and is used interchangeably for the horizontal blank function with bit 5 of OSD control register 2. Accordingly, the horizontal blank function cannot be used simultaneously with the horizontal window function. The display mode to validate the window function is selected by bits 5 to 7 of OSD control register 3. The left boundary is set by left border control registers 1 and 2 (LB1 and LB2), and the right boundary is set by right border control registers 1 and 2 (RB1 and RB2).
Notes 1: When using vertical window, do not set "0016" or "0116" to TB1 at TB2 = "0016." 2: When using horizontal window, do not set LB1 = LB2 = "0016." 3: Horizontal blank and horizontal window, as well as vertical blank and vertical window can not be used simultaneously. 4: When using horizontal window, set as follows: (LB1 + LB2 162) < (RB1 + RB2 162). 5: When using vertical window, set as follows: (TB1 + TB2 162) < (BB1 + BB2 162). 6: When the window function is ON by OSD control registers 1 and 2, the window function of OUT2 is valid in all display mode regardless of setting value of OSD control register 3 (bits 5 to 7). For example, even when make the window function valid in only CC mode, the function of OUT2 is valid in OSD and CDOSD modes.
Left boundary of window Window
Right boundary of window
Top boundary of window
ABCDE F GH I J
CDOSD mode
KL
MNO
CC mode
Window
PQRST U V WX Y
Screen OSD mode Bottom boundary of window
Fig. 8.11.38 Example of window function (When CC Mode Is Valid)
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Top Border Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0 Top border control register 1 (TB1) [Address 021C16] B Name 0 Control bits of to top border 7 (TB10 to TB17) After reset R W Functions Top border position (low-order 8 bits) Indeterminate R W TH (setting value of low-order 2 bits of TB2 162 + setting value of high-order 4 bits of TB1 161 + setting value of low-order 4 bits of TB1 160)
Notes 1: Do not set "0016" or "0116" to the TB1 at TB2 = "0016." 2: TH is cycle of HSYNC. 3: TB2 is top border control register 2.
Fig. 8.11.39 Top Border Control Register 1
Top Border Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0 Top border control register 2 (TB2) [Address 021E16] B Name 0, 1 Control bits of top border (TB20 ,TB21) After reset R W Functions Top border position (high-order 2 bits) Indeterminate R W TH (setting value of low-order 2 bits of TB2 162 + setting value of high-order 4 bits of TB1 161 + setting value of low-order 4 bits of TB1 160)
2 Nothing is assigned. These bits are write disable bits. Indeterminate R -- to When these bits are read out, the values are indeterminate. 7 Notes 1: Do not set "0016" or "0116" to the TB1 at TB2 = "0016." 2: TH is cycle of HSYNC. 3: TB1 is top border control register 1.
Fig. 8.11.40 Top Border Control Register 2
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Bottom Border Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0 Bottom border control register 1 (BB1) [Address 021D16] B Name After reset R W Functions Bottom border position (low-order 8 bits) Indeterminate R W TH (setting value of low-order 2 bits of BB2 162 + setting value of high-order 4 bits of BB1 161 + setting value of low-order 4 bits of BB1 160)
0 Control bits of to bottom border 7 (BB10 to BB17)
Notes 1: Set values fit for the following condition: (TB1 + TB2 162) < (BB1 + BB2 162). 2: TH is cycle of HSYNC. 3: BB2 is bottom border control reigster 2.
Fig. 8.11.41 Bottom Border Control Register 1
Bottom Border Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0 Bottom border control register 2 (BB2) [Address 021F16] B Name 0, 1 Control bits of bottom border (BB20, BB21) After reset R W Functions Indeterminate R W Bottom border position (high-order 2 bits) TH (setting value of low-order 2 bits of BB2 162 + setting value of high-order 4 bits of BB1 161 + setting value of low-order 4 bits of BB1 160)
2 Nothing is assigned. These bits are write disable bits. Indeterminate R -- to 7 When these bits are read out, the values are indeterminate. Notes 1: Set values fit for the following condition: (TB1 + TB2 162) < (BB1 + BB2 162). 2: TH is cycle of HSYNC. 3: BB1 is bottom border control reigster 1.
Fig. 8.11.42 Bottom Border Control Register 2
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Left Border Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0 Left border control register 1 (LB1) [Address 025016]
B 0 1 to 7
Name Control bits of left border (LB10 to LB17)
Functions Left border position (low-order 8 bits) TOSC (setting value of low-order 3 bits of LB2 162 + setting value of high-order 4 bits of LB1 161 + setting value of low-order 4 bits of LB1 160)
After reset R W 1 0 RW
Notes 1: Do not set LB1 = LB2 = "0016." 2: Set values fit for the following condition: (LB1 + LB2 162) < (RB1 + RB2 162). 3: TOSC is OSD oscillation period. 4: LB2 is left border control register 2.
Fig. 8.11.43 Left BorderControl Register 1
Left Border Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0 Left border control register 2 (LB2) [Address 025116]
B 0 to 2
Name Control bits of left border (LB20 to LB22)
Functions Left border position (high-order 3 bits) TOSC (setting value of low-order 3 bits of LB2 162 + setting value of high-order 4 bits of LB1 161 + setting value of low-order 4 bits of LB1 160)
After reset R W 0 RW
3 Nothing is assigned. These bits are write disable bits. to When these bits are read out, the values are indeterminate. 7 Notes 1: Do not set LB1 = LB2 = "0016." 2: Set values fit for the following condition: (LB1 + LB2 162) < (RB1 + RB2 162). 3: TOSC is OSD oscillation period. 4: LB1 is left border control register 1.
0
RW
Fig. 8.11.44 Left Border Control Register 2
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Right Border Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0 Right border control register 1 (RB1) [Address 025216]
B 0 to 7
Name Control bits of right border (RB10 to RB17)
Functions Right border position (low-order 8 bits) TOSC (setting value of low-order 3 bits of RB2 162 + setting value of high-order 4 bits of RB1 161 + setting value of low-order 4 bits of RB1 160)
After reset R W 1 RW
Notes 1: Set values fit for the following condition: (LB1 + LB2 162) < (RB1 + RB2 162). 2: TOSC is OSD oscillation period. 3: RB2 is right border control register 2.
Fig. 8.11.45 Right Border Control Register 1
Right Border Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0 Right border control register 2 (RB2) [Address 025316]
B 0 to 2
Name Control bits of right border (RB20 to RB22)
Functions Right border position (high-order 3 bits) TOSC (setting value of low-order 3 bits of RB2 162 + setting value of high-order 4 bits of RB1 161 + setting value of low-order 4 bits of RB1 160)
After reset R W 1 RW
3 to 7
Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0".
0
RW
Notes 1: Set values fit for the following condition: (LB1 + LB2 162) < (RB1 + RB2 162). 2: TOSC is OSD oscillation period. 3: RB1 is right border control register 1.
Fig. 8.11.46 Right Border Control Register 2
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8.11.15 Blank Function
The blank function can output blank (OUT1) area on all sides (vertical and horizontal) of the screen. The ON/OFF for vertical blank function is performed by bit 5 of the OSD control register 1 and is used to select vertical window function or vertical blank function by bit 6 of the OSD control register 2. Accordingly, the vertical blank function cannot be used simultaneously with the vertical window function. The top border is set by the top border control registers 1 and 2 (TB1, TB2), and the bottom border is set by the bottom border control registers 1 and 2 (BB1, BB2), in 1H units. The ON/OFF for horizontal blank function is performed by bit 4 of the OSD control register 2 and is used interchangeably for the horizontal window function with bit 5 of the OSD control register 2 . Accordingly, the horizontal blank function cannot be used simultaneously with the horizontal window function. The left border is set by the left border control registers 1 and 2 (LB1, LB2) and the right border is set by the right border control registers 1 and 2 (RB1, RB2), in 1TOSC units. The OSD output (except raster) in area with blank output is not deleted. These blank signals are not output in the horizontal/vertical blanking interval.
Notes 1: When using vertical blank, do not set "0016" and "0116" to TB1 at TB2 = "0016." 2: When using horizontal blank, do not set LB1 = LB2 = "0016." 3: Horizontal blank and horizontal window, as well as vertical blank and vertical window can not be used simultaneously. 4: When using horizontal blank, set as follows: (LB1 + LB2 162) < (RB1 + RB2 162). 5: When using vertical blank, set as follows: (TB1 + TB2 162) < (BB1 + BB2 162). 6: When all-blocks display is OFF (bit 0 of OSD control register 1 = "0"), do not use vertical blank.
A
Blank output signal in OUT1 B microcomputer
A
4
Output example of horizontal blank
A'
4
A' LHLH LH
H
OUT1 B
Blank output signal in microcomputer
L H L H L
Output example of top and vertical blank
Fig. 8.11.47 Blank Output Example (When OSD Output is B + OUT1)
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8.11.16 SPRITE OSD Function
This is especially suitable for cursor and other displays as its function allows for display in any position, regardless of the validity of other OSDs or display positions. The sprite font is a RAM font consisting of 16 horizontal dots 5 20 vertical dots, three planes, and three bits of data per dot. Each plane has corresponding color pallet selection bits, and 8 kinds of color pallets can be selected by the plane bit combination (three bits) for each dot. In addition, the selection range (color pallets 0 to 7 and 8 to 15) can be set, per screen, by bit 4 of the OSD control register 3. The color pallet is set in dot units according to the selection range and the OSD RAM (SPRITE) contents from among the selection range. It is possible to arbitrarily add font data by software for the RAM font in the SPRITE font. The SPRITE OSD control register can control SPRITE display, dot size, interrupt position, and interrupt generation factors for the SPRITE OSD. The display position can also be set independently of the block display by the SPRITE horizontal position registers and the sprite horizontal vertical position registers. At this time, the horizontal position is set in 2048 steps in 1TOSC units, and the vertical position is set in 1024 steps in 1TH units. When SPRITE display overlaps with other OSDs, SPRITE display is always given priority. However, the SPRITE display overlaps with the OSD which includes OUT2 output, OUT2 in the OSD is output without masking.
Notes 1: The SPRITE OSD function cnannot output OUT2. 2: When using SPRITE OSD, do not set HS1 < "3016." at HS2 = "0016." 3: When using SPRITE OSD, do not set VS1 = VS2 = "0016."
dot dot 12
......
dot dot 15 16 Line 1 Line 2
Video adjustment Tint Contrast Color tone Picture Brightness - - - - - * * * * * * * * * * l | | | | * * * * * * * * * * + + + + +
Line 19 Line 20
Example of SPRITE font
......
Fig. 8.11.48 SPRITE OSD Display Example
Example of cusor display
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SPRITE OSD Control Register
b7 b6 b5 b4 b3 b2 b1 b0 SPRITE OSD control register (SC) [Address 025816]
B 0
Name SPRITE OSD control bit (SC0) Pre-divide ratio selection bit (SC1) 0: Stopped 1: Operating
Functions
After reset R W 0 RW
1
0: Pre-divide ratio 1 1: Pre-divide ratio 2 b3 0 0 1 1 b2 0: 1Tc 1/2H 1: 1Tc 1H 0: 2Tc 1H 1: 2Tc 2H
0
RW
2, 3 Dot size selection bits (SC2, SC3)
0
RW
4
Interrupt occurrence position selection bit (SC4) XIN/4096 * SPRITE interrupt source switch bit (SC5)
0: After display of horizontal 20 dots 1: After display of horizontal 10 dots or 20 dots 0: XIN/4096 interrupt 1: SPRITE OSD interrupt
0
RW
5
0
RW
6, 7
Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0".
0
R--
Notes 1: Tc : Pre-devided clock period for OSD 2: H : HSYNC
Fig. 8.11.49 SPRITE OSD Control Register
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SPRITE Horizontal Position Register 1
b7 b6 b5 b4 b3 b2 b1 b0 SPRITE horizontal position register 1 (HS1) [Address 025616] B Name 0 Horizontal display to start position control 7 bits of SPRITE OSD (HS10 toHS17) After reset R W Functions Horizontal display start position (low-order 8 bits) Indeterminate R W TOSC (setting value of low-order 2 bits of HS2 162 + setting value of high-order 4 bits of HS1 161 + setting value of low-order 4 bits of HS1 160)
Notes 1: Do not set HS1 < "3016" at HS2 = "0016." 2: TOSC is OSD oscillation period. 3: HS2 is SPRITE horizontal position register 2.
Fig. 8.11.50 SPRITE Horizontal Position Register 1
SPRITE Horizontal Position Register 2
b7 b6 b5 b4 b3 b2 b1 b0 SPRITE horizontal position register 2 (HS2) [Address 025716] B Name 0 Horizontal display to start position control 2 bits of SPRITE OSD (HS20 to HS22) After reset R W Functions Horizontal display start position (high-order 3 bits) Indeterminate R W TOSC (setting value of low-order 2 bits of HS2 162 + setting value of high-order 4 bits of HS1 161 + setting value of low-order 4 bits of HS1 160) 3 Nothing is assigned. These bits are write disable bits. 0 R-- to When these bits are read out, the values are "0." 7
Notes 1: Do not set HS1< "3016" at HS2 = "0016." 2: TOSC is oscillation period. 3: HS1 is SPRITE horizontal position register 1.
Fig. 8.11.51 SPRITE Horizontal Position Register 2
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SPRITE Vertical Position Register 1
b7 b6 b5 b4 b3 b2 b1 b0 SPRITE vertical position register 1 (VS1) [Address 025416]
B 0 1 to 7
Name Vertical display start position control bits of SPRITE OSD (VS10 to VS17)
Functions Vertical display start position (low-order 8 bits) TH (setting value of low-order 2 bits of VS2 162 + setting value of high-order 4 bits of VS1 161 + setting value of low-order 4 bits of VS1 160)
After reset R W 1 0 RW
Notes 1: Do not set "0016" to the VS1 at VS2 = "0016." 2: TH is cycle of HSYNC. 3: VS2 is SPRITE vertical position register 2.
Fig. 8.11.52 PRITE Vertical Position Register 1
SPRITE Vertical Position Register 2
b7 b6 b5 b4 b3 b2 b1 b0 SPRITE vertical position register 2 (VS2) [Address 025516]
B
Name
Functions Vertical display start position (high-order 2 bits) TH (setting value of low-order 2 bits of VS2 162 + setting value of high-order 4 bits of VS1 161 + setting value of low-order 4 bits of VS1 160)
After reset R W 0 RW
0, 1 Vertical start position control bits of SPRITE OSD (VS20, VS21)
2 Nothing is assigned. These bits are write disable bits. to When these bits are read out, the values are "0". 7 Notes 1: Do not set "0016" to the VS1 at VS2 = "0016." 2: TH is cycle of HSYNC. 3: VS1 is SPRITE vertical position register 1.
0
R--
Fig. 8.11.53 SPRITE Vertical Position Register 2
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8.11.17 OSD Output Pin Control
The OSD output pins R(R1), G(G1), B(B1) and OUT1 can also function as ports P52 to P55. Set the corresponding bit of the OSD port control register (address 00CB16) to "0" to specify these pins as OSD output pins, or set it to "1" to specify it as a general-purpose port P5 pin. Pins R0, G0 and B0 can also function as ports P17, P15 and P16, respectively. Set bit 1 of the OSD port control register to "0" to specify these pins as a general-purpose output port P1 pin, or set it to "1" to specify it as OSD output pins. When "0," 4-adjustment-level analog output is output from pins R, G and B. When "1," the value which is converted from the analog to the 2-bit digital is output as follows: the high-order bit is output pins R1, G1 and B1 and the low-order bit is output from pins R0, G0 and B0. The OUT2 can also function as Port P10. Set bit 0 of the port P1 direction register (address 00C316) to "1" (output mode). After that, set bit 6 of the OSD port control register to "1" to specify the pin as OSD output pin, or set it to "0" to specify as port P10 pin. The input polarity of the HSYNC, VSYNC and output polarity of signals R, G, B, OUT1 and OUT2 can be specified with the I/O polarity control register (address 021716). Set a bit to "0" to specify positive polarity; set it to "1" to specify negative polarity (refer to Figure 8.11.18). The OSD port control register is shown in Figure 8.11.54.
Note: When using ports P52 to P54 as general-purpose pins, set bit 2 of OSD control register 2 (address 021516) to "0."
OSD Port Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
OSD port control register (PF) [Address 00CB16]
b 0 1
Name Fix this bit to "0" R, G, B output method selection bit (RGB2BIT)
Functions
After reset R W 0 RW RW
0 : 4-adjustment-level analog is output from pins R, G, B. 1 : Value which is converted from 4-adjustment-level analog to 2-bit digital is output as below: High-order: from R1, G1, B1 Low-order: from R0, G0, B0 0 : R signal output 1 : Port P52 output 0 : G signal output 1 : Port P53 output 0 : B signal output 1 : Port P54 output 0 : OUT1 signal output 1 : Port P55 output 0 : Port P10 signal output 1 : OUT2 output
0
2 3 4 5 6 7
Port P52 output signal selection bit (R) Port P53 output signal selection bit (G) Port P54 output signal selection bit (B) Port P55 output signal selection bit (OUT1) Port P10 output signal selection bit (OUT2) Fix this bit to "0"
0 0 0 0 0 0
RW RW RW RW RW RW
Fig. 8.11.54 OSD Port Control Register
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8.11.18 Raster Coloring Function
An entire screen (raster) can be colored by setting the bits 6 to 0 of the raster color register. Since each of the R, G, B, OUT1, and OUT2 pins can be switched to raster coloring output, 64 raster colors can be obtained. When the character color/the character background color overlaps with the raster color, the color (R, G, B, OUT1, OUT2),specified for the character color/the character background color, takes priority of the raster color. This ensures that the character color/the character background color is not mixed with the raster color. The structure of the raster color register is shown in Figure 8.11.55, the example of raster coloring is shown in Figure 8.11.56.
Note : Raster is not output to the area which includes blank output.
Raster Color Register
b7 b6 b5 b4 b3 b2 b1 b0 Raster color register (RC) [Address 021816]
B
Name
b0 b1
Functions 0 0 1 1 0 0 1 1 0 0 1 1 0: No output (See note) 1: 1/3 VCC 0: 2/3 VCC 1: VCC 0: No output (See note) 1: 1/3 VCC 0: 2/3 VCC 1: VCC 0: No output (See note) 1: 1/3 VCC 0: 2/3 VCC 1: VCC
At reset R W 0 RW
0, 1 Raster color R control bits (RC0, RC1)
2, 3 Raster color G control bits (RC2, RC3)
b3 b2
0
RW
4, 5 Raster color B control bits (RC4, RC5)
b5 b4
0
RW
6 7
Raster color OUT1 control bits (RC6) Raster color OUT2 control bits (RC7)
0: No output 1: Output 0: No output 1: Output
0 0
RW RW
Note: When selecting digital output, VCC is output at any other values except "00."
Fig. 8.11.55 Raster Color Register
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: Character color "RED" (R and OUT1) : Border color "BLACK" (OUT1) : Background color "MAGENTA" (R, B and OUT1) : Raster color "BLUE" (B and OUT1)
A
A'
HSYNC OUT1 R G B
Signals across A-A'
: Character color "RED" (R and OUT1) : Border color "BLACK" (OUT1) : Background color "MAGENTA" (R, B and OUT1) : Raster color "BLUE" (B and OUT1) : Horizontal blank (OUT1)
A
A'
HSYNC OUT1 R G B
Blank control signal in microcomputer
Signals across A-A'
Fig. 8.11.56 Example of Raster Coloring
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8.12 SOFTWARE RUNAWAY DETECT FUNCTION
This microcomputer has a function to decode undefined instructions to detect a software runaway. When an undefined op-code is input to the CPU as an instruction code during operation, the following processing is done. The CPU generates an undefined instruction decoding signal. The device is internally reset because of occurrence of the undefined instruction decoding signal. As a result of internal reset, the same reset processing as in the case of ordinary reset operation is done, and the program restarts from the reset vector. Note, however, that the software runaway detecting function cannot be invalid.
SYNC
Address
PC
?
01,S
01,S-1
01,S-2
FFFE16
FFFF16
ADH, ADL
Data
?
PCH
PCL
PS Reset sequence
ADL
ADH
Undefined instruction decoding signal occurs.Internal reset signal occurs. ?
: Undefined instruction decode : Invalid PC : Program counter S : Stack pointer ADL, ADH : Jump destination address of reset
Fig.8.12.1 Sequence at Detecting Software Runaway Detection
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8.13 RESET CIRCUIT
When the oscillation of a quartz-crystal oscillator or a ceramic resonator is stable and the power source voltage is 5 V 10 %, hold the RESET pin at LOW for 2 s or more, then return is to HIGH. Then, as shown in Figure 8.13.2, reset is released and the program starts form the address formed by using the content of address FFFF16 as the high-order address and the content of the address FFFE16 as the low-order address. The internal state of microcomputer at reset are shown in Figures 8.2.2 to 8.2.7. An example of the reset circuit is shown in Figure 8.13.1. The reset input voltage must be kept 0.9 V or less until the power source voltage surpasses 4.5 V.
Poweron 4.5 V Power source voltage 0 V
Reset input voltage 0 V
0.9 V
Vcc
1 5
M51953AL
RESET
4 3 0.1 F
Vss Microcomputer
Fig.8.13.1 Example of Reset Circuit
XIN RESET Internal RESET SYNC Address Data 32768 count of XIN clock cycle (Note 3) ? ? ? ?
01, S
01, S-1 01, S-2
FFFE
FFFF
ADH, ADL
Reset address from the vector table ? ? ? ADL ADH
Notes 1 : f(XIN) and f() are in the relation : f(XIN) = 2*f (). 2 : A question mark (?) indicates an undefined state that depends on the previous state. 3 : Immediately after a reset, timer 3 and timer 4 are connected by hardware. At this time, "FF 16" is set in timer 3 and "0716" is set to timer 4. Timer 3 counts down with f(XIN)/16, and reset state is released by the timer 4 overflow signal.
Fig.8.13.2 Reset Sequence
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8.14 CLOCK GENERATING CIRCUIT
This microcomputer has 2 built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT). Use the circuit constants in accordance with the resonator manufacturer's recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. However, an external feed-back resistor is needed between XCIN and XCOUT. When using XCIN-XCOUT as sub-clock, clear bits 5 and 4 of the clock source control register to "0." To supply a clock signal externally, input it to the XIN (XCIN) pin and make the XOUT (XCOUT) pin open. When not using XCIN clock, connect the XCIN to VSS and make the XCOUT pin open. After reset has completed, the internal clock is half the frequency of XIN. Immediately after poweron, both the XIN and XCIN clock start oscillating. To set the internal clock to low-speed operation mode, set bit 7 of the CPU mode register (address 00FB16) to "1."
(2) Low-speed Mode If the internal clock is generated from the sub-clock (XCIN), a low power consumption operation can be realized by stopping only the main clock XIN. To stop the main clock, set bit 6 (CM6) of the CPU mode register (00FB16) to "1." When the main clock XIN is restarted, the program must allow enough time to for oscillation to stabilize. Note that in low-power-consumption mode the XCIN-XCOUT drivability can be reduced, allowing even lower power consumption. To reduce the XCIN-XCOUT drivability, clear bit 5 (CM5) of the CPU mode register (00FB16) to "0." At reset, this bit is set to "1" and strong drivability is selected to help the oscillation to start. When an STP instruction is executed, set this bit to "1" by software before executing.
Microcomputer
8.14.1 OSCILLATION CONTROL
(1) Stop Mode The built-in clock generating circuit is shown in Figure 120. When the STP instruction is executed, the internal clock stops at HIGH. At the same time, timers 3 and 4 are connected by hardware and "FF16" is set in timer 3 and "0716" is set in timer 4. Select f(XIN)/16 or f(XCIN)/ 16 as the timer 3 count source (set both bit 0 of the timer mode register 2 and bit 6 at address 00C716 to "0" before the execution of the STP instruction). Moreover, set the timer 3 and timer 4 interrupt enable bits to disabled ("0") before execution of the STP instruction. The oscillator restarts when external interrupt is accepted. However, the internal clock keeps its HIGH level until timer 4 overflows, allowing time for oscillation stabilization when a ceramic resonator or a quartz-crystal oscillator is used. (2) Wait Mode When the WIT instruction is executed, the internal clock stops in the HIGH level but the oscillator continues running. This wait state is released at reset or when an interrupt is accepted (Note). Since the oscillator does not stop, the next instruction can be executed at once.
Note: In the wait mode, the following interrupts are invalid. * VSYNC interrupt * OSD interrupt * All timers interrupts using TIM2 pin input as count source * All timers interrupt using TIM3 pin input as count source * Data slicer interrupt * Multi-master I2C-BUS interface interrupt * f(XIN)/4096 interrupt * All timer interrupts using f(XIN)/2 or f(XCIN)/2 as count source * All timer interrupts using f(XIN)/4096 or f(XCIN)/4096 as count source * A-D conversion interrupt * SPRITE OSD interrupt
XCIN
Rf
XCOUT
XIN
XOUT
Rd
CCIN
CCOUT
CIN
COUT
Fig.8.14.1 Ceramic Resonator Circuit Example
Microcomputer XCIN XCOUT XIN Open External oscillation circuit or external pulse Vcc Vss XOUT Open External oscillation circuit Vcc Vss
Fig.8.14.2 External Clock Input Circuit Example
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XCIN
XCOUT
XIN
OSC1 oscillating mode selection bits (See notes 1, 4) XOUT "1" 1/2 "0" Internal system clock selection bit (See notes 1, 3) 1/8 "1" "0"
Timer 3 count stop bit (See notes 1, 2) Timer 3
Timer 4 count stop bit (See notes 1, 2) Timer 4
Timer 3 count source selection bit (See notes 1, 2) Timing (Internal clock)
Main clock (XIN-XOUT) stop bit (Notes 1, 3) Internal system clock selection bit (Notes 1, 3) Q S S Q Q S
Reset STP instruction
R
STP instruction
WIT instruction
R
R
Reset Interrupt disable flag I Interrupt request
Notes 1 : The value at reset is "0." 2 : Refer to the structure of timer mode register 2. 3 : Refer to the structure of CPU mode register (next page). 4 : Refer to the structure of clock source control register.
Fig.8.14.3 Clock Generating Circuit Block Diagram
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Reset
High-speed operation start mode
WIT instruction 8 MHz oscillating 32 kHz oscillating is stopped (HIGH) Timer operating 8 MHz oscillating 32 kHz oscillating f() = 4 MHz Interrupt External INT, timer interrupt, or SI/O interrupt
STP instruction 8 MHz stopped 32 kHz stopped is stopped (HIGH) Interrupt (Note 1) External INT CM7 = 0
CM7 = 1
WIT instruction 8 MHz oscillating 32 kHz oscillating is stopped (HIGH) Timer operating (Note 3) 8 MHz oscillating 32 kHz oscillating f() = 16 kHz Interrupt
STP instruction 8 MHz stopped 32 kHz stopped is stopped (HIGH) Interrupt (Note 2)
CM6 = 0 The program must allow time for 8 MHz oscillation to stabilize
CM6 = 1
8 MHz stopped 32 kHz oscillating is stopped (HIGH) Timer operating (Note 3)
WIT instruction 8 MHz stopped 32 kHz oscillating f() = 16 kHz Interrupt
STP instruction 8 MHz stopped 32 kHz stopped = stopped (HIGH ) Interrupt (Note 2)
CPU mode register (Address : 00FB16) CM6 : Main clock (XIN-XOUT) stop bit 0 : Oscillating 1 : Stopped CM7 : Internal system clock selection bit 0 : XIN-XOUT selected (high-speed mode) 1 : XCIN-XCOUT selected (low-speed mode)
The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. The indicates the internal clock. Notes 1: When the STP state is ended, a delay of approximately 4 ms is automatically generated by timer 3 and timer 4. 2: The delay after the STP state ends is approximately 1 s. 3: When the internal clock divided by 8 is used as the timer count source, the frequency of the count source is 2 kHz.
Fig.8.14.4 State Transitions of System Clock
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8.15 DISPLAY OSCILLATION CIRCUIT
The OSD oscillation circuit has a built-in clock oscillation circuits, so that a clock for OSD can be obtained simply by connecting an LC, a ceramic resonator, or a quartz-crystal oscillator across the pins OSC1 and OSC2. Which of the sub-clock or the OSD oscillation circuit is selected by setting bits 5 and 4 of the clock control register (address 021616).
8.17 ADDRESSING MODE
The memory access is reinforced with 17 kinds of addressing modes. Refer to SERIES 740 User's Manual for details.
8.18 MACHINE INSTRUCTIONS
There are 71 machine instructions. Refer to SERIES 740 User's Manual for details.
9. PROGRAMMING NOTES
* The divide ratio of the timer is 1/(n+1). * Even though the BBC and BBS instructions are executed immediately after the interrupt request bits are modified (by the program), those instructions are only valid for the contents before the modification. At least one instruction cycle is needed (such as an NOP) between the modification of the interrupt request bits and the execution of the BBC and BBS instructions. * After the ADC and SBC instructions are executed (in the decimal mode), one instruction cycle (such as an NOP) is needed before the SEC, CLC, or CLD instruction is executed. * An NOP instruction is needed immediately after the execution of a PLP instruction. * In order to avoid noise and latch-up, connect a bypass capacitor ( 0.1F) directly between the VCC pin-VSS pin, AVCC pin-VSS pin, and the VCC pin-CNVSS pin, using a thick wire.
OSC1
OSC2
L C1 C2
Fig.8.15.1 Display Oscillation Circuit
8.16 AUTO-CLEAR CIRCUIT
When a power source is supplied, the auto-clear function will operate by connecting the following circuit to the RESET pin.
Circuit example 1
Vcc
RESET
Vss
Circuit example 2
RESET
Vcc
Vss
Note : Make the level change from "L" to "H" at the point at which the power source voltage exceeds the specified voltage.
Fig.8.16.1 Auto-clear Circuit Example
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10. ABSOLUTE MAXIMUM RATINGS
Symbol VCC, (AVCC) VI VI Parametear Power source voltage VCC ( ) ...M37280EKSP Input voltage CNVSS Input voltage P00-P07, P10-P17, P20-P27, P30, P31, P40-P46, P64, P63, P70-P72, XIN, HSYNC, VSYNC, ______ RESET P00-P07, P10-P17, P20-P27, P30-P32, P47, P50-P57, P60-P62, P65-P67, SOUT, SCLK, XOUT, OSC2 P52-P55, P10, P03, P15-P17, P20-P27, P30, P31 P52-P57, P10, , P03, P15-P17, P20-P27, P65-P67, SOUT, SCLK P11-P14 P00-P02, P04-P07, P32, P47, P50 P51, P60-P62 P30, P31 Conditions All voltages are based on VSS. Output transistors are cut off. Ratings -0.3 to 6 -0.3 to 6 -0.3 to VCC + 0.3 Unit V V V
VO
Output voltage
-0.3 to VCC + 0.3
V
IOH IOL1 IOL2 IOL3 IOL4 Pd Topr Tstg
Circuit current Circuit current Circuit current Circuit current
0 to 1 (See note 1) 0 to 2 (See note 2) 0 to 6 (See note 2) 0 to 1 (See note 2) 0 to 10 (See note 3) 550 -10 to 70 -40 to 125
mA mA mA mA mA mW C C
Circuit current Power dissipation Operating temperature Storage temperature
Ta = 25 C
11. RECOMMENDED OPERATING CONDITIONS (Ta = -10 C to 70 C, VCC = 5 V 10 %, unless otherwise noted)
Symbol VCC, (AVCC) VCC, (AVCC) VSS VIH1 Parameter Power source voltage (See note 4), During CPU, OSD, data slicer operation ( ) ...M37280EKSP RAM hold voltage (when clock is stopped) ( ) ...M37280EKSP Power source voltage HIGH input voltage P00-P07, P10-P17, P20-P27, P30, P31, P40-P46, P63, P64, P70-P72, HSYNC, VSYNC, RESET, XIN HIGH input voltage SCL1, SCL2, SDA1, SDA2 LOW input voltage P00-P07, P10-P17, P20-P27, P30, P31, P40-P46, P63, P64, P70-P72 LOW input voltage SCL1, SCL2, SDA1, SDA2 LOW input voltage (See note 6) RESET, XIN, OSC1, HSYNC, VSYNC, INT1, INT2, INT3, TIM2, TIM3, SCLK, SIN HIGH average output current (See note 1) P52-P55, P10, P03, P15-P17, P20-P27, P30, P31 LOW average output current (See note 2) P51-P57, P10, P03, P15-P17, P20-P27, SOUT, SCLK, P47, P65-P67 LOW average output current (See note 2) P11-P14 LOW average output current (See note 2) P00-P02, P04-P07, P32, P47, P50, P51, P60-P62 LOW average output current (See note 3) P30, P31 Oscillation frequency (for CPU operation) (See note 5) XIN Oscillation frequency (for sub-clock operation) XCIN Oscillation frequency (for OSD) OSC1 LC oscillating mode Ceramic oscillating mode Load resistance During R,G,B analog output Input frequency TIM2, TIM3, INT1, INT2, INT3 Input frequency SCLK Input frequency SCL1, SCL2 Input frequency Horizontal sync. signal of video signal Input amplitude video signal CVIN Min. 4.5 2.0 0 0.8VCC Limits Typ. 5.0 0 Max. 5.5 5.5 0 VCC Unit V V V V
VIH2 VIL1 VIL2 VIL3 IOH IOL1 IOL2 IOL3 IOL4 f(XIN) f(XCIN) fosc RL fhs1 fhs2 fhs3 fhs4 VI
0.7VCC 0 0 0
VCC 0.4 VCC 0.3 VCC 0.2 VCC 1 2 6 1 10 8.1 35 27.0 27.5 100 1 400 16.206 2.5
V V V V mA mA mA mA mA MHz kHz MHz
7.9 29 11.0 25.5 20.0
8.0 32 26.5
15.262 1.5
15.734 2.0
kHz MHz kHz kHz V
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12. ELECTRIC CHARACTERISTICS (VCC = 5 V 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = -10 C to 70 C, unless otherwise noted)
Symbol ICC Parameter Power source current System operation Test conditions Min. VCC = 5.5 V, CRT OFF f(XIN) = 8 MHz Data slicer OFF CRT ON (digital output) Data slicer ON CRT ON (analog output) Data slicer ON VCC = 5.5 V, f(XIN) = 0, f(XCIN) = 32 kHz, OSD OFF, Data slicer OFF, Low-power dissipation mode set (CM5 = "0", CM6 = "1") Wait mode VCC = 5.5 V, f(XIN) = 8 MHz VCC = 5.5 V, f(XIN) = 0, f(XCIN) = 32kHz, Low-power dissipation mode set (CM5 = "0", CM6 = "1") Stop mode VCC = 5.5 V, f(XIN) = 0 f(XCIN) = 0 P52-P55, P10, P03, P15-P17, VCC = 4.5 V P20-P27, P30, P31 IOH = -0.5 mA SOUT, SCLK, P00-P07, P10, VCC = 4.5 V P15-P17, P20-P27,P32, IOL = 0.5 mA P47, P50-P57, P60-P62, P65-P67 P30, P31 VCC = 4.5 V IOL = 10.0 mA P11-P14 VCC = 4.5 V IOL = 3 mA IOL = 6 mA VCC = 5.0 V Limits Typ. 15 30 50 60 Max. 30 50 70 200 A 1 2 25 4 100 mA A Unit mA Test circuit
1 2.4
10
V V 2
VOH VOL
HIGH output voltage LOW output voltage
0.4
V
LOW output voltage LOW output voltage
3.0 0.4 0.6 1.3
2
VT+ - VT- Hysteresis (See note 6) RESET, HSYNC, VSYNC, INT1,INT2, INT3, TIM2, TIM3, SIN, SCLK, SCL1, SCL2, SDA1, SDA2 HIGH input leak current RESET, P00-P07, P10-P17, P20- IIZH P27, P30, P31, P40-P46, P63, P64, P70-P72, HSYNC, VSYNC LOW input leak current RESET, P00-P07, P10-P17, IZL P20-P27, P30, P31, P40-P46, P63, P64, P70-P72, HSYNC, VSYNC I2C-BUS*BUS switch connection resistor RBS (between SCL1 and SCL2, SDA1 and SDA2)
0.5
V 3
VCC = 5.5 V VI = 5.5 V VCC = 5.5 V VI = 0 V VCC = 4.5 V
5
A 4
5
mA
130
5
Notes 1: The total current that flows out of the IC must be 20 or less. 2: The total input current to IC (IOL1 + IOL2 + IOL3) must be 20 mA or less. 3: The total average input current for ports P30, P31 to IC must be 10 mA or less. 4: Connect 0.1 F or more capacitor externally between the power source pins VCC-VSS (and AVCC-VSS ) so as to reduce power source noise. Also connect 0.1 F or more capacitor externally between the pins VCC-CNVSS. ( ) ...M37280EKSP 5: Use a quartz-crystal oscillator or a ceramic resonator for the CPU oscillation circuit. When using the data slicer, use 8 MHz. 6: P16, P41-P44 have the hysteresis when these pins are used as interrupt input pins or timer input pins. P11-P14 have the hysteresis when these pins are used as multi-master I2C-BUS interface ports. P17, P46 and P72 have the hysteresis when these pins are used as serial I/O pins. 7: When using the sub-clock, set fCLK < fCPU/3. 8: Pin names in each parameter is described as below. (1) Dedicated pins: dedicated pin names. (2) Duble-/triple-function ports * When the same limits: I/O port name. * When the limits of functins except ports are different from I/O port limits: function pin name.
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1
A
Power source voltage
2
4.5V
Icc XIN 8.00 MHz OSC1 XOUT XCIN OSC2 32 kHz XCOUT
Vss V VOH or VOL IOH or IOL
Each output pin
Vcc
Vcc
Vss
Pin VCC is confirmed the operation and tested the current with a ceramic resonator.
After setting each output pin to HIGH level when measuring VOH and to LOW level when measuring VOL, each pin is measured.
3
5.0V
4
5.5V
Vcc
Vcc
IIZH or IIZL A
Each output pin
Each output pin
Vss
Vss
5.5V or 0V
5
4.5V
Vcc SCL1 or SDA1
IBS A
RBS
SCL2 or SDA2 Vss
VBS
RBS = VBS/IBS
Fig.12.1 Test circuit
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13. ANALOG R, G, B OUTPUT CHARACTERISTICS
(VCC = 5 V 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = -10 C to 70 C, unless otherwise noted) Symbol RO VOE TST Output resistance Output deviation Settling time Parameter Test conditions VCC = 4.5 V VCC = 5.5 V VCC = 4.5 V, load capacity of 10 pF, load resistor of 20 k, 70 % DC level Min. Limits Typ. Max. 2 0.5 50 Unit k V ns
V CC
V0E 70%VP-P VP-P 30%VP-P V0E TST
2 / 3 V CC
1 / 3 V CC
V SS
Fig.13.1 Analog R, G, B, Output Characteristics
14. A-D CONVERTER CHARACTERISTICS
(VCC = 5 V 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = -10 C to 70 C, unless otherwise noted) Symbol -- -- TCONV RLADDER VIA Parameter Resolution Absolute accuracy (excludig guantization error) Conversion time Ladder resistor Analog input voltage Test conditions Min. Limits Typ. Max. 8 2.5 12.5 VREF Unit bits LSB s k V
Vcc = 5 V 12.25 25 0
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15. MULTI-MASTER I2C-BUS BUS LINE CHARACTERISTICS
Symbol tBUF tHD; STA tLOW tR tHD; DAT tHIGH tF tSU; DAT tSU; STA tSU; STO Parameter Bus free time Hold time for START condition LOW period of SCL clock Rising time of both SCL and SDA signals Data hold time HIGH period of SCL clock Falling time of both SCL and SDA signals Data set-up time Set-up time for repeated START condition Set-up time for STOP condition Standard clock mode High-speed clock mode Unit Max. Min. Min. Max. 1.3 4.7 s 0.6 4.0 s 1.3 4.7 s 1000 20+0.1Cb 300 ns 0 0 0.9 s 4.0 0.6 s 300 20+0.1Cb 300 ns 250 100 ns 4.7 0.6 s 4.0 0.6 s
Note: Cb = total capacitance of 1 bus line
SDA tHD;STA tSU;STO
tBUF tLOW P SCL S
tR
tF Sr P
tHD;STA
tHD;DAT
tHIGH
tSU;DAT
tSU;STA
S : Start condition Sr : Restart condition P : Stop condition
Fig.15.1 Definition Diagram of Timing on Multi-master I2C-BUS
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
16. PROM PROGRAMMING METHOD
The built-in PROM of the One Time PROM version (blank) and the built-in EPROM version can be read or programmed with a generalpurpose PROM programmer using a special programming adapter. Product M37280EKSP Name of Programming Adapter PCA7401
The PROM of the One Time PROM version (blank) is not tested or screened in the assembly process nor any following processes. To ensure proper operation after programming, the procedure shown in Figure 29.1 is recommended to verify programming.
Programming with PROM programmer
Screening (Caution) (150C for 40 hours)
Verification with PROM programmer
Functional check in target device
Caution : The screening temperature is far higher than the storage temperature. Never expose to 150C exceeding 100 hours.
Fig. 16.1 Programming and Testing of One Time PROM Version
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17. DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM production: * Mask ROM Order Confirmation Form * Mark Specification Form * Data to be written to ROM, in EPROM form (32-pin DIP Type 27C101, three identical copies) or FDK
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18. APPENDIX Pin Configuration (TOP VIEW)
HSYNC VSYNC P40AD4 P41/INT2 P42/TIM2 P43/TIM3 P24/AD3 P25/AD2 P26/AD1 P27/AD5 P00/PWM4 P50/PWM7 P01/PWM5 P47 P02/PWM6 P51 P17/SIN/R0 P32 P44/INT1 P56 P45/SOUT P57 P46/SCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P52/R/R1 P53/G/G1 P54/B/B1 P55/OUT1 P04/PWM0 P05/PWM1 P60 P06/PWM2 P61 P07/PWM3 P62 P20 P21 P22 P23 P10/OUT2 P65 P11/SCL1 P66 P12/SCL2 P67 P13/SDA1 P14/SDA2 P15/G0 P16/INT3/B0 P03/PWM7 P30/AD7 P31/AD8 RESET P64/OSC2/XCOUT P63/OSC1/XCIN VCC
M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
( )...M37280EKSP (AVCC
) NC HLF/AD6 P72/(SIN)
P71/VHOLD P70/CVIN CNVSS XIN XOUT VSS
Outline 64P4B
Note: Only 24th pin is NC pin of M37280MFH/ MKH-XXXSP. This pin is AVcc pin of M37280EKSP. But NC pin of M37280MFH/MKH-XXXSP is not connect in the IC. You can apply to Vcc.
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Memory Map
000016 00BF16 00C016 00FF16 010016 020016 025816 02C016 02FF16 030016 053F16
OSD RAM (SPRITE) (120 bytes) (See note 1) OSD RAM (character) (1536 bytes) (See note 2) Zero page
1000016 1080016
Not used
RAM (1472 bytes) for M37280MKH-XXXSP and M37280EKSP
RAM (1024 bytes) for M37280MFHXXXSP
SFR1 area
OSD ROM
SFR2 area Not used
(character font) (20400 bytes)
ROM correction function Vector 1 : address 02C016 Vector 2 : address 02E016 Not used
157FF16 Not used 1800016
06FF16 070016 07A716 080016
Not used
OSD ROM (color dot font) (9672 bytes)
0FFF16 100016
1ACFF16
Not used
1B00016
ROM (60K bytes) Expansion ROM (20K bytes) for M37280MKH-XXXSP
Bank 11 Bank 12 Bank 13 Bank 14
1C00016 1D00016 1E00016 1F00016
FF0016 FFDE16 FFFF16
and M37280EKSP
Interrupt vector area
Special page
Bank 15 1FFFF16 Notes 1: Refer to Table 8.11.4 OSD RAM (SPRITE). 2: Refer to Tables 8.11.5 and 8.11.6 OSD RAM (character).
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Memory Map of Special Function Register (SFR)
s SFR1 area (addresses C016 to DF16)

:
Name
:
Function bit
0 : "0" immediately after reset 1 : "1" immediately after reset ? : Indeterminate immediately after reset
: No function bit 0 : Fix to this bit to "0" (do not write to "1") 1 : Fix to this bit to "1" (do not write to "0") Bit allocation
b7
Address C016 C116 C216 C316 C416 C516 C616 C716 C816 C916 CA16 CB16 CC16 CD16 CE16 CF16 D016 D116 D216 D316 D416 D516 D616 D716 D816 D916 DA16 DB16 DC16 DD16 DE16 DF16
Register
State immediately after reset
b0 b7 b0
Port P0 (P0) Port P0 direction register (D0) Port P1 (P1) Port P1 direction register (D1) Port P2 (P2) Port P2 direction register (D2) Port P3 (P3) Port P3 direction register (D3) Port P4 (P4) Port P4 direction register (D4) Port P5 (P5) OSD port control register (PF) Port P6 (P6) Port P7 (P7) OSD control register 1 (OC 1) Horizontal position register (HP) Block control register 1 (BC 1) Block control register 2 (BC 2) Block control register 3 (BC 3) Block control register 4 (BC 4) Block control register 5 (BC 5) Block control register 6 (BC 6) Block control register 7 (BC 7) Block control register 8 (BC 8) Block control register 9 (BC 9) Block control register 10 (BC10) Block control register 11 (BC11) Block control register 12 (BC12) Block control register 13 (BC13) Block control register 14 (BC14) Block control register 15 (BC15) Block control register 16 (BC16)
P6IM T3CS
0 0
OUT2 OUT1
B
G
R
RGB 2BIT
0 0 0 0
OC17 OC16 OC15 OC14 OC13 OC12 OC11 OC10 HP17 HP16 HP15 HP14 HP13 HP12 HP11 HP10 BC16 BC15 BC14 BC13 BC12 BC11 BC10 BC26 BC25 BC24 BC23 BC22 BC21 BC20 BC36 BC35 BC34 BC33 BC32 BC31 BC30 BC46 BC45 BC44 BC43 BC42 BC41 BC40 BC56 BC55 BC54 BC53 BC52 BC51 BC50 BC66 BC65 BC64 BC63 BC62 BC61 BC60 BC76 BC75 BC74 BC73 BC72 BC71 BC70 BC86 BC85 BC84 BC83 BC82 BC81 BC80 BC96 BC95 BC94 BC93 BC92 BC91 BC90
BC106 BC105 BC104 BC103 BC102 BC101 BC100 BC116 BC115 BC114 BC113 BC112 BC111 BC110 BC126 BC125 BC124 BC123 BC122 BC121 BC120 BC136 BC135 BC134 BC133 BC132 BC131 BC130 BC146 BC145 BC144 BC143 BC142 BC141 BC140 BC156 BC155 BC154 BC153 BC152 BC151 BC150 BC166 BC165 BC164 BC163 BC162 BC161 BC160
? 0016 ? 0016 ? 0016 ? 0016 ? 0016 ? 0016 ? 00 0016 0016 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
?
?
?
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
s SFR1 area (addresses E016 to FF16)

:
Name :
Function bit
0 : "0" immediately after reset 1 : "1" immediately after reset ? : Indeterminate immediately after reset
: No function bit 0 : Fix to this bit to "0" (do not write to "1") 1 : Fix to this bit to "1" (do not write to "0") Address E016 E116 E216 E316 E416 E516 E616 E716 E816 E916 EA16 EB16 EC16 ED16 EE16 EF16 F016 F116 F216 F316 F416 F516 F616 F716 F816 F916 FA16 FB16 FC16 FD16 FE16 FF16 Register
b7 Data slicer control register 1 (DSC1) Data slicer control register 2 (DSC2) Caption data register 1 (CD1) Caption data register 2 (CD2) Caption data register 3 (CD3) Caption data register 4 (CD4) Caption Position register (CPS) Data slicer test register 2 Data slicer test register 1
Sync signal counter register (HC) Clock run-in detect register (CRD) Data clock position register (DPS)
Bit allocation 0 0 0 0 0 0
DSC12 DSC11 DSC10
State immediately after reset
b0 b7 b0
DSC25 DSC24 DSC23
0
DSC20
?
0
?
CDL17 CDL16 CDL15 CDL14 CDL13 CDL12 CDL11 CDL10 CDH17 CDH16 CDH15 CDH14 CDH13 CDH12 CDH11 CDH10 CDL27 CDL26 CDL25 CDL24 CDL23 CDL22 CDL21 CDL20 CDH27 CDH26 CDH25 CDH24 CDH23 CDH22 CDH21 CDH20 CPS7 CPS6 CPS5 CPS4 CPS3 CPS2 CPS1 CPS0
0
0
?
0016 0016
HC5 HC4 HC3 HC2 HC1 HC0
CRD7 CRD6 CRD5 CRD4 CRD3 DPS7 DPS6 DPS5 DPS4 DPS3
0
0
?
0
0
1
BK7 BK6 0 Bank control register (BK) 0 BK3 BK2 BK1 BK0 A-D conversion register (AD) A-D control register (ADCON) 0 0 ADVREF ADSTR ADIN2 ADIN1 ADIN0 Timer 1 (T1) Timer 2 (T2) Timer 3 (T3) Timer 4 (T4) Timer mode register 1 (TM1) TM17 TM16 TM15 TM14 TM13 TM12 TM11 TM10 Timer mode register 2 (TM2) TM27 TM26 TM25 TM24 TM23 TM22 TM21 TM20 D7 D6 D5 D4 D3 D2 D1 D0 I2C data shift register (S0) SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW 2C address register (S0D) I MST TRX BB PIN AL AAS AD0 LRB I2C status register (S1) 10BIT BSEL BSEL I2C control register (S1D) SAD ALS ESO BC2 BC1 BC0 ACK FAST I2 C clock control register (S2) ACK BIT MODE CCR4 CCR3 CCR2 CCR1 CCR0 CM7 CM6 CM5 1 CPU mode register (CM) 1 CM2 0 0 Interrupt request register 1 (IREQ1) OSDR TM4R TM3R TM2R TM1R ADR VSCR Interrupt request register 2 (IREQ2) 0 TM56R IICR IN2R CKR SIOR DSR IN1R CK0 Interrupt control register 1 (ICON1) ADE VSCE OSDE TM4E TM3E TM2E TM1E Interrupt control register 2 (ICON2) TM56S TM56E IICE IN2E CKE SIOE DSE IN1E
0
?
0
0
0
0
0016 0? 0016 0016 0016 0016 00 0016 0016 ?? 0016 0916 ? 0016 ? 01 FF16 0716 FF16 0716 0016 0016 ? 0016 10 0016 0016 3C16 0016 0016 0016 0016
?
0
?
0
0
0
?
?
?
0
0
0
0
0
?
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
s SFR2 area (addresses 20016 to 21F16)

:
Name
Function bit
0 : "0" immediately after reset 1 : "1" immediately after reset ? : Indeterminate immediately after reset
: : No function bit
0 : Fix to this bit to "0" (do not write to "1") 1 : Fix to this bit to "1" (do not write to "0") Address 20016 20116 20216 20316 20416 20516 20616 20716 20816 20916 20A16 20B16 20C16 20D16 20E16 20F16 21016 21116 21216 21316 21416 21516 21616 21716 21816 21916 21A16 21B16 21C16 21D16 21E16 21F16 Register
b7 PWM0 register (PWM0) PWM1 register (PWM1) PWM2 register (PWM2) PWM3 register (PWM3) PWM4 register (PWM4) PWM5 register (PWM5) PWM6 register (PWM6) PWM7 register (PWM7)
Bit allocation
b0 b7
State immediately after reset
b0
PWM mode register 1 (PN) PN4 PN3 PN0 PWM mode register 2 (PW) PW7 PW6 PW5 PW4 PW3 PW2 PW1 PW0 ROM correction address 1 (high-order) ROM correction address 1 (low-order) ROM correction address 2 (high-order) ROM correction address 2 (low-order) ROM correction enable register (RCR) Test register Interrupt input polarity register (IP) Serial I/O mode register (SM) Serial I/O register (SIO) OSD control register 2(OC2) Clock control register (CS) I/O polarity control register (PC) Raster color register (RC) OSD control register 3(OC3) Timer 5 (TM5) Timer 6 (TM6) Top border control register 1 (TB1) Bottom border control register 1 (BB1) Top border control register 1 (TB2) Bottom border control register 1 (BB2)
TB17 TB16 TB15 TB14 TB13 TB12 TB11 TB10 BB17 BB16 BB15 BB14 BB13 BB12 BB11 BB10 TB21 TB20 BB21 BB20 OC27 OC26 OC25 OC24 OC23 OC12 OC21 OC20
AD/INT3 SEL AD/INT3 PC7 SEL AD/INT3 SEL AD/INT3 INT3 SEL POL AD/INT3 SEL AD/INT3 SEL
RE5
RE3 RE2 RCR1 RCR0 0 0 RE1
00 16
INT3 POL3 RE5 POL2 POL1 RE2 RE3 POL INT3 SM6 RE5 SM4 RE3 RE2 SM3 SM2 POL SM5
RE1 SM1 RE1 SM0
INT3 0 POL INT3 PC6 POL INT3 POL
0
0
0
RE2 CS2
RE1 CS0 CS1 PC1 RE1 PC0 RC1 RE1 RC0
PC5 RE5 PC4
RE3 RE2 PC2
RE5 RC4 RC3 RE2 RE3 RC2
OC37 OC36 OC35 OC34 OC33 RE2 RE1 OC30 RE3 OC32 OC31
? ? ? ? ? ? ? ? ? ? 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 ? 0016 0016 8016 0016 0016 0716 FF16 ? ? ? ?
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
s SFR2 area (addresses 22016 to 23F16)
:
Name
0 : "0" immediately after reset 1 : "1" immediately after reset ? : Indeterminate immediately after reset
:
Function bit
: No function bit 0 : Fix to this bit to "0" (do not write to "1") 1 : Fix to this bit to "1" (do not write to "0") Bit allocation
b7
1 2 3
Address 22016 22116 22216 22316 22416 22516 22616 22716 22816 22916 22A16 22B16 22C16 22D16 22E16 22F16 23016 23116 23216 23316 23416 23516 23616 23716 23816 23916 23A16 23B16 23C16 23D16 23E16 23F16
Register
(VP1 1 ) (VP1 2 )
b0 b7
State immediately after reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
b0
Vertical position register 1 Vertical position register 1 Vertical position register 1 Vertical position register 1 Vertical position register 1 Vertical position register 1 Vertical position register 1 Vertical position register 1 Vertical position register 1 Vertical position register 1 Vertical position register 1 Vertical position register 1 Vertical position register 1 Vertical position register 1 Vertical position register 1 Vertical position register 1 Vertical position register 2 Vertical position register 2 Vertical position register 2 Vertical position register 2 Vertical position register 2 Vertical position register 2 Vertical position register 2 Vertical position register 2 Vertical position register 2 Vertical position register 2 Vertical position register 2 Vertical position register 2 Vertical position register 2 Vertical position register 2 Vertical position register 2 Vertical position register 2
VP117 VP116 VP115 VP114 VP113 VP112 VP111 VP110 VP127 VP126 VP125 VP124 VP123 VP122 VP121 VP120 VP137 VP136 VP135 VP134 VP133 VP132 VP131 VP130 VP147 VP146 VP145 VP144 VP143 VP142 VP141 VP140 VP157 VP156 VP155 VP154 VP153 VP152 VP151 VP150 VP167 VP166 VP165 VP164 VP163 VP162 VP161 VP160 VP177 VP176 VP175 VP174 VP173 VP172 VP171 VP170 VP187 VP186 VP185 VP184 VP183 VP182 VP181 VP180 VP197 VP196 VP195 VP194 VP193 VP192 VP191 VP190
(VP1 3 ) 4 (VP1 4 ) 5 (VP1 5 ) 6 (VP1 6 ) (VP1 7 ) 8 (VP1 8 ) 9 (VP1 9 )
7
) 10 (VP1 10 ) VP1107 VP1106 VP1105 VP1104 VP1103 VP1102 VP1101 VP1100 ) 11 (VP1 11 ) VP1117 VP1116 VP1115 VP1114 VP1113 VP1112 VP1111 VP1110 ) 12 (VP1 12 ) VP1127 VP1126 VP1125 VP1124 VP1123 VP1122 VP1121 VP1120 (VP1 13 ) 14 (VP1 14 ) 15 (VP1 15 ) 16 (VP1 16 ) 1 (VP2 1 )
13 2 (VP2 2 ) 3 (VP2 3 )
VP1137 VP1136 VP1135 VP1134 VP1133 VP1132 VP1131 VP1130 ) VP1147 VP1146 VP1145 VP1144 VP1143 VP1142 VP1141 VP1140 ) VP1157 VP1156 VP1155 VP1154 VP1153 VP1152 VP1151 VP1150 ) VP1167 VP1166 VP1165 VP1164 VP1163 VP1162 VP1161 VP1160 ) VP211 VP210 VP221 VP220 VP231 VP230 VP241 VP240 VP251 VP250 VP261 VP260 VP271 VP270 VP281 VP280 VP291 VP290 VP2101 VP2100 VP2111 VP2110 VP2121 VP2120 VP2131 VP2130 VP2141 VP2140 VP2151 VP2150 VP2161 VP2160
(VP2 4 ) 5 (VP2 5 ) 6 (VP2 6 )
4 7 (VP2 7 ) 8 (VP2 8 ) 9 (VP2 9 )
(VP2 10 ) 11 (VP2 11 ) 12 (VP2 12 )
10
(VP2 13 ) 14 (VP2 14 ) 15 (VP2 15 ) 16 (VP2 16 )
13
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
s SFR2 area (addresses 24016 to 25816)

:
Name
Function bit
0 : "0" immediately after reset 1 : "1" immediately after reset ? : Indeterminate immediately after reset
: : No function bit
0 : Fix to this bit to "0" (do not write to "1") 1 : Fix to this bit to "1" (do not write to "0") Address 24016 24116 24216 24316 24416 24516 24616 24716 24816 24916 24A16 24B16 24C16 24D16 24E16 24F16 25016 25116 25216 25316 25416 Register
b7 Color pallet register 1 (CR1) Color pallet register 2 (CR2) Color pallet register 3 (CR3) Color pallet register 4 (CR4) Color pallet register 5 (CR5) Color pallet register 6 (CR6) Color pallet register 7 (CR7) Color pallet register 9 (CR9) Color pallet register10 (CR10) Color pallet register 11 (CR11) Color pallet register 12 (CR12) Color pallet register 13 (CR13) Color pallet register 14 (CR14) Color pallet register 15 (CR15) Left border control register 1 (LB1) Left border control register 2 (LB2) Right border control register 1 (RB1) Right border control register 2 (RB2)
SPRITE vertical position register 1 (VS1)
Bit allocation
State immediately after reset
b0 b7 b0
CR16 CR15 CR14 CR13 CR12 CR11 CR10 CR26 CR25 CR24 CR23 CR22 CR21 CR20 CR36 CR35 CR34 CR33 CR32 CR31 CR30 CR46 CR45 CR44 CR43 CR42 CR41 CR40 CR56 CR55 CR54 CR53 CR52 CR51 CR50 CR66 CR65 CR64 CR63 CR62 CR61 CR60 CR76 CR75 CR74 CR73 CR72 CR71 CR70 CR96 CR95 CR94 CR93 CR92 CR91 CR90
CR106 CR105 CR104 CR103 CR102 CR101 CR100 CR116 CR115 CR114 CR113 CR112 CR111 CR110 CR126 CR125 CR124 CR123 CR122 CR121 CR120 CR136 CR135 CR134 CR133 CR132 CR131 CR130 CR146 CR145 CR144 CR143 CR142 CR141 CR140 CR156 CR155 CR154 CR153 CR152 CR151 CR150 LB17 LB16 LB15 LB14 LB13 LB12 LB11 LB10 LB22 LB21 LB20 RB17 RB16 RB15 RB14 RB13 RB12 RB11 RB10 RB22 RB21 RB20 VS17 VS16 VS15 VS14 VS13 VS12 VS11 VS10 VS21 VS20 HS17 HS16 HS15 HS14 HS13 HS12 HS11 HS10 HS22 HS21 HS20 SC5 SC4 SC3 SC2 SC1 SC0
25516 SPRITE vertical position register 2 (VS2) 25616 SPRITE horizontal position register 1 (HS1) 25716 SPRITE horizontal position register 2 (HS2) 25816 SPRITE OSD control register (SC)
0
0
0
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0116 0016 FF16 0716 ? 0016 ? 00 0016
?
?
?
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
Internal State of Processor Status Register and Program Counter at Reset
:
Name
0 : "0" immediately after reset 1 : "1" immediately after reset ? : Indeterminate immediately after reset
Function bit
: : No function bit
0 : Fix to this bit to "0" (do not write to "1") 1 : Fix to this bit to "1" (do not write to "0") Register
b7 Processor status register (PS) Program counter (PCH) Program counter (PCL)
Bit allocation
b0 b7
State immediately after reset
b0
N
V
T
B
D
I
Z
C
?????1?? Contents of address FFFF16 Contents of address FFFE16
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
Structure of Register
The figure of each register structure describes its functions, contents at reset, and attributes as follows:

CPU Mode Register
b7 b6 b5 b4 b3 b2 b1 b0 11 00
Bit attributes (Note 2) Bits Values immediately after reset release (Note 1)
CPU mode register (CPUM) (CM) [Address 00FB B Name 0, 1 Processor mode bits (CM0, CM1) Functions
b1 b0 16]
After reset R W 0 RW
0 0 1 1
0: Single-chip mode 1: 0: Not available 1: 0 1 1 0 RW RW RW RW
2
Stack page selection bit (See note) (CM2)
0: 0 page 1: 1 page
3, 4 Fix these bits to "1." Nothing is assigned. This bit is write disable bit. When this bit is read out, the value is "0." b7 b6 6, 7 Clock switch bits (CM6, CM7) 0 0: f(XIN) = 8 MHz 0 1: f(XIN) = 12 MHz 1 0: f(XIN) = 16 MHz 1 1: Do not set : Bit in which nothing is assigned 5
Notes 1: Values immediately after reset release 0 ******************"0" after reset release 1 ******************"1" after reset release Indeterminate***Indeterminate after reset release 2: Bit attributes******The attributes of control register bits are classified into 3 types : read-only, write-only and read and write. In the figure, these attributes are represented as follows : W******Write R******Read W ******Write enabled R ******Read enabled - ******Write disabled - ******Read disabled ******"0" can be set by software, but "1" cannot be set.
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
Address 00C116, 00C316, 00C516
Port Pi Direction Register
b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (Di) (i = 0,1,2) [Addresses 00C116, 00C316, 00C516]
B 0 1 2 3 4 5 6 7
Name Port Pi direction register
Functions 0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode
After reset R W 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW
Address 00C716
Port P3 Direction Register
b7 b6 b5 b4 b3 b2 b1 b0 Port P3 direction register (D3) [Address 00C7 16]
B 0 1
Name Port P3 direction register
Functions 0 : Port P30 input mode 1 : Port P30 output mode 0 : Port P31 input mode 1 : Port P31 output mode
After reset R W 0 0 RW RW
2 to 5 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0." 6 7 Timer 3 count source selection bit (T3SC) Ports P63, P64 selection bits (P6IM) Refer to Timer section. Refer to clock control register (address 021616).
0 0 0
R-- RW RW
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
Address 00C916
Port P4 Direction Register
b7 b6 b5 b4 b3 b2 b1 b0 Port P3 direction register (D4) [Address 00C7 16]
B 0
Name Fix this bit to "0"
Functions
After reset R W
0 0
RW RW
1 to 4 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0." 5 6 7 Port P4 direction register 0 : Port P45 input mode 1 : Port P45 output mode 0 : Port P46 input mode 1 : Port P47 output mode Nothing is assigned. This bit is write disable bit. When this bit is read out, the values is "0."
0 0 0
R-- RW RW
Address 00CB16
OSD Port Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
OSD port control register (PF) [Address 00CB16]
b 0 1
Name Fix this bit to "0" R, G, B output method selection bit (RGB2BIT)
Functions
After reset R W 0 RW RW
0 : 4-adjustment-level analog is output from pins R, G, B. 1 : Value which is converted from 4-adjustment-level analog to 2-bit digital is output as below: High-order: from R1, G1, B1 Low-order: from R0, G0, B0 0 : R signal output 1 : Port P52 output 0 : G signal output 1 : Port P53 output 0 : B signal output 1 : Port P54 output 0 : OUT1 signal output 1 : Port P55 output 0 : Port P10 signal output 1 : OUT2 output
0
2 3 4 5 6 7
Port P52 output signal selection bit (R) Port P53 output signal selection bit (G) Port P54 output signal selection bit (B) Port P55 output signal selection bit (OUT1) Port P10 output signal selection bit (OUT2) Fix this bit to "0"
0 0 0 0 0 0
RW RW RW RW RW RW
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
Address 00CE16
OSD Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0 OSD control register 1 (OC1) [Address 00CE16] After reset Functions 0 : All-blocks display off 0 1 : All-blocks display on 0 : Normal scan mode 0 1 : Bi-scan mode 0 2 Border type selection 0 : All bordered 1 : Shadow bordered (See note 2) bit (OC12) 0 3 Flash mode selection 0 : Color signal of character background part does not flash bit (OC13) 1 : Color signal of character background part flashes B 0 Name OSD control bit (OC10) (See note 1) 1 Scan mode selection bit (OC11) 4 Automatic solid space control bit (OC14) 0 : OFF 1 : ON 0 0 RW RW RW RW RW
RW RW
5 Vertical window/blank 0 : OFF control bit (OC15) 1 : ON 6, 7 Layer mixing control bits (OC16, OC17) (See note 3)
b7 b6
0 0: Logic sum (OR) of layer 1's color and layer 2's color 0 1: Layer 1's color has priority 1 0: Layer 2's color has priority 1 1: Do not set.
0
RW
Notes 1 : Even this bit is switched during display, the display screen remains unchanged until a rising (falling) of the next VSYNC. 2 : Shadow border is output at right and bottom side of the font. 3 : OUT2 is always ORed, regardless of values of these bits.
Address 00CF16
Horizontal Position Register
b7 b6 b5 b4 b3 b2 b1 b0 Horizontal position register (HP) [Address 00CF16] After reset R W Name Functions Horizontal display start positions 0 Control bits of horizontal 0 RW 4TOSC to display start positions 1 (setting value of high-order 4 bits 16 (HP0 to HP7) 7 +setting value of low-order 4 bits 160 ) B Notes 1. The setting value synchronizes with the VSYNC. 2. TOSC = OSD oscillation period.
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
Address 00D016 to 00DF16
Block Control Register i
b7 b6 b5 b4 b3 b2 b1 b0 Block control register i (BCi) (i=1 to 16) [Addresses 00D016 to 00DF16] B Name
b1 b0 Functions
Functions 0 0 1 1 0 1 0 1 Display OFF OSD mode CC mode CDOSD mode
After reset R W Indeterminate R W
0, 1 Display mode selection bits (BCi0, BCi1)
2 Border control bit 0 : Border OFF (BCi2) 1 : Border ON 3, 4 Dot size selection bits (BCi3, BCi4)
b6 b5 b4 0 0 1 1 0 0 1 1 0 0 0 0 1 1 b3 Pre-divide ratio 0 1 0 1 1 0 1 2 0 1 0 1 0 3 1 0 1 Dot size 1Tc 1/2H 1Tc 1H 2Tc 2H 3Tc 3H 1Tc 1/2H 1Tc 1H 2Tc 2H 3Tc 3H 1.5Tc 1/2H (See note 3) 1.5Tc 1H (See note 3) 1Tc 1/2H 1Tc 1H 2Tc 2H 3Tc 3H
Indeterminate R W Indeterminate R W
0
0
0
1
5, 6 Pre-divide ratio selection bit (BCi5, BCi6)
Indeterminate R W
1
1
1
1
7
Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is indeterminate.
Indeterminate R --
Notes 1: Tc : OSD clock cycle divided in pre-divide circuit 2: H : HSYNC 3: This character size is available only in Layer 2. At this time, set layer 1's pre-divide ratio = 2, layer 1's horizontal dot size = 1Tc.
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
Address 00E016
Data Slicer Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0 00000 Data slicer control register 1(DSC1) [Address 00E016] B Name Functions 0: Stopped 1: Operating 0: F2 1: F1 0: Video signal 1: HSYNC signal After reset R W 0 0 0 0 RW RW RW RW
0 Data slicer and timing signal generating circuit control bit (DSC10) 1 Selection bit of data slice reference voltage generating field (DSC11) 2 Reference clock source selection bit (DSC12) 3 to Fix these bits to "0." 7
Definition of fields 1 (F1) and 2 (F2) F1: Hsep Vsep F2: Hsep Vsep
Address 00E116
Data Slicer Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Data slicer control register 2 (DSC2) [Address 00E116]
B 0
Name Caption data latch completion flag 1 (DSC20)
Functions
After reset
RW
0: Data is not latched yet and a Indeterminate R -- clock-run-in is not determined. 1: Data is latched and a clock-run-in is determined. 0 Read-only 0: F2 1: F1 0: Method (1) 1: Method (2) RW
1 2 3 4
Fix this bit to "0." Test bit Field determination flag(DSC23) Vertical synchronous signal (Vsep) generating method selection bit (DSC24)
Indeterminate R -- Indeterminate R -- 0 RW
5 6 7
0: Match V-pulse shape determination flag (DSC25) 1: Mismatch Fix this bit to "0." Test bit Read-only
Indeterminate R -- 0 RW
Indeterminate R --
Definition of fields 1 (F1) and 2 (F2) F1: Hsep Vsep F2: Hsep Vsep
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
Address 00E616
Caption Position Register
b7 b6 b5 b4 b3 b2 b1 b0 Caption Position Register (CPS) [Address 00E616]
B 0 to 4 5
Name Caption position bits(CPS0 to CPS4) Caption data latch completion flag 2 (CPS5)
Functions
After reset 0
RW RW
0: Data is not latched yet and a Indeterminate R -- clock-run-in is not determined. 1: Data is latched and a clock-run-in is determined. Refer to the corresponding Table (Table 12.10.1). 0 RW
6, 7 Slice line mode specification bits (in 1 field) (CPS6, CPS7)
Address 00E916
Sync Signal Counter Register
b7 b6 b5 b4 b3 b2 b1 b0 Sync pulse counter register (HC) [Address 00E916]
B 0 to 4 5
Name Count value (HC0 to HC4)
Functions
After reset Indeterminate
RW R--
Count source (HC5)
0: HSYNC signal 1: Composite sync signal
0
RW
6, 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0."
0
R--
Address 00EA16
Clock Run-in Detect Register
b7 b6 b5 b4 b3 b2 b1 b0 Clock run-in detect register (CRD) [Address 00EA16]
B 0 to 2 3 to 7 Test bits
Name Read-only
Functions
After reset R W 0 R--
Clock run-in detection bit(CRD3 to CRD7)
Number of reference clocks to be counted in one clock run-in pulse period.
0
R--
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
Address 00EB16
Data Clock Position Register
b7 b6 b5 b4 b3 b2 b1 b0 0 0 1 Data clock position register (DPS) [Address 00EB16]
B 0
Name Fix these bits to "1."
Functions
After reset R W 1 0 1 0 RW RW RW
1,2 Fix this bit to "0." 3 4 to 7 Data clock position set bits (DPS3 to DPS7)
Address 00ED16
Bank Control Register
b7 b6 b5 b4 b3 b2 b1 b0
00
Bank control register (BK) [Address 00ED16]
B 0 to 3
Name
Functions
After reset R W 0 RW
Bank Bank number is selected (bank 11 to 15) selection bits (BK0 to BK3)
4, 5 Fix these bits to "0". 6, 7 Bank control bits (BK6, BK7) b7 b6 Bank ROM Address 100016 level access 0 Not used Read out from extra area (programmable) 1 0 Used Read out the data from area specified by the bank selection bits Read out from extra area 1 1 Used (data-dedicated)
0 0
RW RW
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
Address 00EF16
A-D Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
A-D control register (ADCON) [Address 00EF16]
B
0 to 2
Name
Analog input pin selection bits (ADIN0 to ADIN2) b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1
Functions
b0 0 : AD1 1 : AD2 0 : AD3 1 : AD4 0 : AD5 1 : AD6 0 : AD7 1 : AD8
After reset R W
0
RW
3 4 5 6 7
A-D conversion completion bit (ADSTR) VCC connection selection bit (ADVREF) Fix this bit to "0."
0: Conversion in progress 1: Convertion completed 0: OFF 1: ON
1 0 0 Indeterminate
RW RW RW R-- RW
Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is indeterminate. Fix this bit to "0."
0
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
Address 00F416
Timer Mode Register 1
b7 b6 b5 b4 b3 b2 b1 b0 Timer mode register 1 (TM1) [Address 00F416] B 0 1 Name Timer 1 count source selection bit 1 (TM10) Timer 2 count source selection bit 1 (TM11) After reset R W Functions 0: f(XIN)/16 or f(XCIN)/16 (Note) 0 RW 1: Count source selected by bit 5 of TM1 0: Count source selected by bit 4 of TM1 1: External clock from TIM2 pin 0: Count start 1: Count stop 0: Count start 1: Count stop 0 0 0 0 0 0 0 RW RW RW RW RW RW RW
2 Timer 1 count stop bit (TM12) 3 Timer 2 count stop bit (TM13)
4 Timer 2 count source 0: f(XIN)/16 or f(XCIN)/16 (See note) selection bit 2 (TM14) 1: Timer 1 overflow 5 Timer 1 count source selection bit 2 (TM15) 6 Timer 5 count source selection bit 2 (TM16) 7 Timer 6 internal count source selection bit (TM17) 0: f(XIN)/4096 or f(XCIN)/4096 (See note) 1: External clock from TIM2 pin 0: Timer 2 overflow 1: Timer 4 overflow 0: f(XIN)/16 or f(XCIN)/16 (See note) 1: Timer 5 overflow
Note: Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register.
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
Address 00F516
Timer Mode Register 2
b7 b6 b5 b4 b3 b2 b1 b0 Timer mode register 2 (TM2) [Address 00F516] B Name 0 Timer 3 count source selection bit (TM20) Functions (b6 at address 00C716) 0 1 0 1 1, 4 Timer 4 count source selection bits (TM21, TM24) b4 0 0 1 1 b0 0 : f(XIN)/16 or f(XCIN)/16 (See note) 0 : f(XCIN) 1: 1 : External clock from TIM3 pin b1 0 : Timer 3 overflow signal 1 : f(XIN)/16 or f(XCIN)/16 (See note) 0 : f(XIN)/2 or f(XCIN)/2 (See note) 1 : f(XCIN) 0 RW After reset R W 0 RW
2 Timer 3 count stop bit (TM22) 3 Timer 4 count stop bit (TM23) 5 Timer 5 count stop bit (TM25) 6 Timer 6 count stop bit (TM26)
0: Count start 1: Count stop 0: Count start 1: Count stop 0: Count start 1: Count stop 0: Count start 1: Count stop
0 0 0 0
RW RW RW RW
7 Timer 5 count source 0: f(XIN)/16 or f(XCIN)/16 (See note) RW 0 1: Count source selected by bit 6 selection bit 1 of TM1 (TM27) Note: Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register.
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
Address 00F616
I2C Data Shift Register
b7 b6 b5 b4 b3 b2 b1 b0 I2C data shift register 1 (S0) [Address 00F616]
B 0 to 7
Name D0 to D7
Functions This is an 8-bit shift register to store receive data and write transmit data.
2
After reset
RW
Indeterminate R W
Note: To write data into the I C data shift register after setting the MST bit to "0" (slave mode), keep an interval of 8 machine cycles or more.
Address 00F716
I2C Address Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C address register (S0D) [Address 00F716] B
0 1 to 7
Name
Read/write bit (RBW) Slave address (SAD0 to SAD6) 0: Read 1: Write
Functions
After reset R W
0 0
R-- RW
The address data transmitted from the master is compared with the contents of these bits.
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
Address 00F816
I2C Status Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C status register (S1) [Address 00F816] B
0 1 2 3 4 5
Name
Last receive bit (LRB) (See note) General call detecting flag (AD0) (See note) Slave address comparison flag (AAS) (See note) Arbitration lost detecting flag (AL) (See note) interface interrupt request bit (PIN) Bus busy flag (BB) I2C-BUS
Functions
0 : Last bit = "0 " 1 : Last bit = "1 " (See note)
After reset R W
Indeterminate 0 0
R-- R-- R-- R-- RW RW RW
0 : No general call detected 1 : General call detected (See note) 0 : Address match 1 : Address mismatch 0 : Not detected 1 : Detected (See note)
0 0 0 0
(See note) 0 : Interrupt request issued 1 : No interrupt request issued 0 : Bus free 1 : Bus busy
6, 7 Communication mode specification bits (TRX, MST)
b7 0 0 1 1
b6 0 : Slave recieve mode 1 : Slave transmit mode 0 : Master recieve mode 1 : Master transmit mode
Note : These bits and flags can be read out, but cannnot be written.
Address 00F916
I2C Control Register
b7 b6 b5 b4 b3 b2 b1 b0 I2C control register (S1D) [Address 00F916]
B
0 to 2
Name
Bit counter (Number of transmit/recieve bits) (BC0 to BC2) b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1
Functions
b0 0: 8 1: 7 0: 6 1: 5 0: 4 1: 3 0: 2 1: 1
After reset R W
0
RW
3 4 5
I2C-BUS interface use enable bit (ESO) Data format selection bit(ALS) Addressing format selection bit (10BIT SAD)
0: Disabled 1: Enabled 0: Addressing format 1: Free data format 0: 7-bit addressing format 1: 10-bit addressing format b7 b6 Connection port (See note) 0 0: None 0 1: SCL1, SDA1 1 0: SCL2, SDA2 1 1: SCL1, SDA1, SCL2, SDA2
0 0 0 0
RW RW RW RW
6, 7 Connection control bits 2 between I C-BUS interface and ports (BSEL0, BSEL1)
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
Address 00FA16
I2C Clock Control Register
b7 b6 b5 b4 b3 b2 b1 b0 I2C clock control register (S2) [Address 00FA16]
B
0 to 4
Name
Functions
High speed clock mode
After reset R W
0
SCL frequency control bits Setup value of Standard clock (CCR0 to CCR4) mode CCR4-CCR0 00 to 02 03 04 05 06 1D 1E 1F
RW
Setup disabled Setup disabled Setup disabled Setup disabled 100 83.3
500/CCR value
333 250 400 (See note) 166
1000/CCR value
...
17.2 16.6 16.1
34.5 33.3 32.3 0
(at = 4 MHz, unit : kHz) 5 SCL mode specification bit (FAST MODE) ACK bit (ACK BIT) ACK clock bit (ACK) 0: Standard clock mode 1: High-speed clock mode 0: ACK is returned. 1: ACK is not returned. 0: No ACK clock 1: ACK clock
RW RW RW
6 7
0 0
Note: At 400 kHz in the high-speed clock mode, the duty is as below . "0" period : "1" period = 3 : 2 In the other cases, the duty is as below. "0" period : "1" period = 1 : 1
Address 00FB16
CPU Mode Register
b7 b6 b5 b4 b3 b2 b1 b0 11 00 CPU mode register (CM) [Address 00FB16] B Name 0, 1 Processor mode bits (CM0, CM1) Functions
b1 b0
After reset R W 0 RW
2 Stack page selection bit (CM2) (See note) 3, 4 Fix these bits to "1." 5 XCOUT drivability selection bit (CM5) 6 Main Clock (XIN-XOUT) stop bit (CM6) 7 Internal system clock selection bit (CM7)
0 0: Single-chip mode 0 1: 1 0: Not available 1 1: 0: 0 page 1: 1 page
1 1
RW RW RW RW
0: LOW drive 1: HIGH drive 0: Oscillating 1: Stopped
1 0
0: XIN-XOUT selected (high-speed mode) 1: XCIN-XCOUT selected (low-speed mode) Note: This bit is set to "1" after the reset release.
0
RW
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
Address 00FC16
Interrupt Request Register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) [Address 00FC16] B 0 1 2 3 4 5 6 7 After reset Name Functions 0 : No interrupt request issued Timer 1 interrupt 0 request bit (TM1R) 1 : Interrupt request issued Timer 2 interrupt 0 : No interrupt request issued 0 request bit (TM2R) 1 : Interrupt request issued Timer 3 interrupt 0 : No interrupt request issued 0 request bit (TM3R) 1 : Interrupt request issued Timer 4 interrupt 0 0 : No interrupt request issued request bit (TM4R) 1 : Interrupt request issued OSD interrupt request 0 : No interrupt request issued 0 bit (OSDR) 1 : Interrupt request issued VSYNC interrupt 0 0 : No interrupt request issued request bit (VSCR) 1 : Interrupt request issued A-D conversion * INT3 0 : No interrupt request issued 0 interrupt request bit (ADR) 1 : Interrupt request issued Nothing is assigned. This bit is a write disable bit. 0 When this bit is read out, the value is "0." RW R R R R R R R R--
: "0" can be set by software, but "1" cannot be set.
Address 00FD16
Interrupt Request Register 2
b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt request register 2 (IREQ2) [Address 00FD16] Name INT1 interrupt 0 request bit (IN1R) 1 Data slicer interrupt request bit (DSR) 2 Serial I/O interrupt request bit (SIOR) 3 f(XIN)/4096 * SPRITE OSD interrupt request bit (CKR) 4 INT2 interrupt request bit (IN2R) B Functions After reset 0 : No interrupt request issued 0 1 : Interrupt request issued 0 : No interrupt request issued 0 1 : Interrupt request issued 0 : No interrupt request issued 0 1 : Interrupt request issued 0 : No interrupt request issued 0 1 : Interrupt request issued 0 : No interrupt request issued 0 1 : Interrupt request issued 0 : No interrupt request issued 0 5 Multi-master I2C-BUS interrupt request bit (IICR) 1 : Interrupt request issued 6 Timer 5 * 6 interrupt 0 : No interrupt request issued 0 request bit (TM56R) 1 : Interrupt request issued 7 Fix this bit to "0." 0 : "0" can be set by software, but "1" cannot be set. RW R R R R R R R RW
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
Address 00FE16
Interrupt Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address 00FE16] B 0 Functions After reset 0 0 : Interrupt disabled 1 : Interrupt enabled 0 1 Timer 2 interrupt 0 : Interrupt disabled enable bit (TM2E) 1 : Interrupt enabled 0 2 Timer 3 interrupt 0 : Interrupt disabled enable bit (TM3E) 1 : Interrupt enabled 0 3 Timer 4 interrupt 0 : Interrupt disabled enable bit (TM4E) 1 : Interrupt enabled 0 4 OSD interrupt enable bit 0 : Interrupt disabled (OSDE) 1 : Interrupt enabled 5 VSYNC interrupt enable 0 0 : Interrupt disabled bit (VSCE) 1 : Interrupt enabled 6 A-D conversion * INT3 0 0 : Interrupt disabled interrupt enable bit (ADE) 1 : Interrupt enabled 0 7 Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0." Name Timer 1 interrupt enable bit (TM1E) RW RW RW RW RW RW RW RW R--
Address 00FF16
Interrupt Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 2 (ICON2) [Address 00FF16] B 0 1 2 3 4 5 6 7 Name INT1 interrupt enable bit (IN1E) Data slicer interrupt enable bit (DSE) Serial I/O interrupt enable bit (SIOE) f(XIN/4096 * SPRITE OSD interrupt enable bit (CKE) INT2 interrupt enable bit (IN2E) Multi-master I2C-BUS interface interrupt enable bit (IICE) Timer 5 * 6 interrupt enable bit (TM56E) Timer 5 * 6 interrupt switch bit (TM56S) After reset Functions 0 0: Interrupt disabled 1: Interrupt enabled 0 0: Interrupt disabled 1: Interrupt enabled 0 0: Interrupt disabled 1: Interrupt enabled 0 0: Interrupt disabled 1: Interrupt enabled 0: Interrupt disabled 0 1: Interrupt enabled 0 0: Interrupt disabled 1: Interrupt enabled 0 0: Interrupt disabled 1: Interrupt enabled 0 0: Timer 5 1: Timer 6 RW RW RW RW RW RW RW RW RW
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
Address 020A16
PWM Mode Register 1
b7 b6 b5 b4 b3 b2 b1 b0 PWM mode register 1 (PN) [Address 020A16] B 0 Name PWM counts source selection bit (PN0) Functions 0 : Count source supply 1 : Count source stop After reset 0 0 0 0 0 RW RW R-- RW RW R--
1, 2 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0." 3 4 PWM output polarity selection bit (PN3) P03/PWM7 output selection bit (PN4) 0 : Positive polarity 1 : Negative polarity 0 : P03 output 1 : PWM7 output
5 to 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0."
Address 020B16
PWM Mode Register 2
b7 b6 b5 b4 b3 b2 b1 b0 PWM mode register 2 (PW) [Address 020B16] B Name 0 P04/PWM0 output selection bit (PW0) 1 P05/PWM1 output selection bit (PW1) 2 P06/PWM2 output selection bit (PW2) 3 P07/PWM3 output selection bit (PW3) 4 P00/PWM4 output selection bit (PW4) 5 P01/PWM5 output selection bit (PW5) 6 P02/PWM6 output selection bit (PW6) 7 P50/PWM7 output selection bit (PW7) Functions 0 : P04 output 1 : PWM0 output 0 : P05 output 1 : PWM1 output 0 : P06 output 1 : PWM2 output 0 : P07 output 1 : PWM3 output 0 : P00 output 1 : PWM4 output 0: P01 output 1: PWM5 output 0: P02 output 1: PWM6 output 0: P50 output 1: PWM7 output After reset R W 0 RW 0 0 0 0 0 0 0 RW RW RW RW RW RW RW
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
Address 021016
ROM Correction Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
00
ROM correction enable register (RCR) [Address 021016] B
0 1
Name
Vector 1 enable bit (RCR0) Vector 2 enable bit (RCR1)
Functions
0: Disabled 1: Enabled 0: Disabled 1: Enabled
After reset R W
0 0
RW RW RW R--
2, 3 Fix these bits to "0."
0
4 to 7
Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0."
0
Address 021216
Interrupt Input Polarity Register
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt input polarity register (IP) [Address 021216]
B
Name
Functions
After reset 0 0 0
RW R-- RW RW
0 to 2 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0." 3 4 INT1 polarity switch bit (POL1) INT2 polarity switch bit (POL2) 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity
5 6 7
Nothing is assigned. This bit is write disable bit. When this bit is read out, the value is "0." INT3 polarity switch bit (POL3) A-D conversion * INT3 interrupt source selection bit (AD/INT3SEL) 0 : Positive polarity 1 : Negative polarity 0 : INT3 interrupt 1 : A-D conversion interrupt
0 0 0
R-- RW RW
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
Address 021316
Serial I/O Mode Register
b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O mode register (SM) [Address 021316] B Name b1 0 0 1 1 Functions b0 0: f(XIN)/8 or f(XCIN)/8 1: f(XIN)/16 or f(XCIN)/16 0: f(XIN)/32 or f(XCIN)/32 1: f(XIN)/64 or f(XCIN)/64 After reset R W 0 RW
0, 1 Internal synchronous clock selection bits (SM0, SM1)
2 3
Synchronous clock selection bit (SM2) Port function selection bit (SM3)
0: External clock 1: Internal clock 0: P11, P13 1: SCL1, SDA1 0: P12, P14 1: SCL2, SDA2 0: LSB first 1: MSB first 0: P17 is SIN pin. 1: P72 is SIN pin.
0 0
RW RW
4 Port function selection bit (SM4) 5 6 7 Transfer direction selection bit (SM5) SIN pin switch bit (SM6)
0 0 0 0
RW RW RW R--
Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0."
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
Address 021516
OSD Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0 OSD control register 2 (OC2) [Address 021516]
B
Name
Functions b1 b0 Layer 1 0 0 CC, OSD, CDOSD 0 1 CC, OSD 1 0 CC, CDOSD 1 1 CC Layer 2
At reset R W 0 RW
0, 1 Display layer selection bits (OC20, OC21)
2 3 4 5
CDOSD OSD CDOSD OSD (See note) R, G, B signal output 0: Digital output selection bit(OC22) 1: Analog output (4 gradations)
0 0 0 0
RW RW RW RW
Solid space output bit 0: OUT1 output (OC23) 1: OUT2 output Horizotal window/blank coutrol bit (OC24) Window/blank selection bit 1 (horizontal) (OC25) Window/blank selection bit 2 (vertical) (OC26) OSD interrupt request selection bit (OC27) 0: OFF 1: ON 0: Horizontal blank function 1: Horizontal window function 0: Vertical blank function 1: Vertical window function 0: At completion of layer 1 block display 1: At completion of layer 2 block display
6
0
RW
7
0
RW
Note: When setting bit 1 of the OSD port control register to "1," the value which is converted from the 4-adjustment-level analog to the 2-bit digital is output regardless of this bit value as follows : the high-order bit (R1, G1 and B1) is output from pins P52, P53 and P54, and the low-order bit is (R0, G0 and B0) output from pins P17, P15 and P16. And besides, when not using OSD function, the low-power dissipation can realize by setting this bit to "0."
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
Address 021616
Clock Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0000
Clock control register (CS) [Address 021616]
B 0 1, 2
Name Clock selection bit (CS0)
Functions 0: Data slicer clock 1: OSC1 clock
After reset R W 0 0 RW RW
OSC1 oscillating mode b2 b1 selection bits (CS1, CS2) 0 0: 32kHz oscillating mode. 0 1: Used as input port of P63 and P64 (See note 1). 1 0: LC oscillating mode 1 1: Ceramic * quartz-crystal oscillating mode Fix these bits to "0." Test bit (See note 2)
3 to 6 7
0 0
RW RW
Note 1: Set bit 7 of address 00C716 to "1", when OSC1 and OSC2 are used as P63 and P64. 2: Be sure to set bit 7 to "0" for program of the mask and the EPROM versions. For the emulator MCU version (M37280ERSS), be sure to set bit 7 to "1" when using the data slicer clock for software debugging.
Address 021716
I/O Polarity Control Register
b7 b6 b5 b4 b3 b2 b1 b0 I/O polarity control register (PC) [Address 021716]
B 0 1 2 3 4 5 6
Name HSYNC input polarity switch bit (PC0) VSYNC input polarity switch bit (PC1) R, G, B output polarity switch bit (PC2)
Functions 0 : Positive polarity input 1 : Negative polarity input 0 : Positive polarity input 1 : Negative polarity input 0 : Positive polarity output 1 : Negative polarity output
After reset R W 0 0 0 0 0 0 0 RW RW RW R-- RW RW RW
Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0". OUT1 output polarity 0 : Positive polarity output switch bit (PC4) 1 : Negative polarity output OUT2 output polarity switch bit (PC5) Display dot line selection bit (PC6) (See note) 0 : Positive polarity output 1 : Negative polarity output 0:" " 1:" " " at even field " at odd field " at even field " at odd field
7
Field determination flag(PC7)
0 : Even field 1 : Odd field
1
R--
Note: Refer to Fig. 12.11.19.
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
Address 021816
Raster Color Register
b7 b6 b5 b4 b3 b2 b1 b0 Raster color register (RC) [Address 021816]
B
Name
b0 b1
Functions 0 0 1 1 0 0 1 1 0 0 1 1 0: No output (See note) 1: 1/3 VCC 0: 2/3 VCC 1: VCC 0: No output (See note) 1: 1/3 VCC 0: 2/3 VCC 1: VCC 0: No output (See note) 1: 1/3 VCC 0: 2/3 VCC 1: VCC
At reset R W 0 RW
0, 1 Raster color R control bits (RC0, RC1)
2, 3 Raster color G control bits (RC2, RC3)
b3 b2
0
RW
4, 5 Raster color B control bits (RC4, RC5)
b5 b4
0
RW
6 7
Raster color OUT1 control bits (RC6) Raster color OUT2 control bits (RC7)
0: No output 1: Output 0: No output 1: Output
0 0
RW RW
Note: When selecting digital output, VCC is output at any other values except "00."
Address 021916
OSD Control Register 3
b7 b6 b5 b4 b3 b2 b1 b0 OSD control register 3 (OC3) [Address 021916]
B 0
Name CC mode character color selection bit (OC30)
Functions 0: Color code 0 to 7 1: Color code 8 to 15
b1 b1
After reset R W 0 0 RW RW
1, 2 CC mode character background color selection bits (OC31, OC32) (See note) 3 4 5 6 7 CDOSD mode character color selection bit (OC33) SPRITE color selection bit (OC34) OSD mode window control bit (OC35) CC mode window control bit (OC36) CDOSD mode window control bit (OC37)
0 0 1 1
0: Color code 0 to 3 1: Color code 4 to 7 0: Color code 8 to 11 1: Color code 12 to 15
0: Color code 0 to 7 1: Color code 8 to 15 0: Color code 0 to 7 1: Color code 8 to 15 0: Window OFF 1: Window ON 0: Window OFF 1: Window ON 0: Window OFF 1: Window ON
0 0 0 0 0
RW RW RW RW RW
Note: Color pallet 8 is always selected for solid space (when OUT1 output is selected), regardress of value of this register.
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
Address 021C16
Top Border Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0 Top border control register 1 (TB1) [Address 021C16] B Name 0 Control bits of to top border 7 (TB10 to TB17) After reset R W Functions Top border position (low-order 8 bits) Indeterminate R W TH (setting value of low-order 2 bits of TB2 162 + setting value of high-order 4 bits of TB1 161 + setting value of low-order 4 bits of TB1 160)
Notes 1: Do not set "0016" or "0116" to the TB1 at TB2 = "0016." 2: TH is cycle of HSYNC. 3: TB2 is top border control register 2.
Address 021D16
Bottom Border Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0 Bottom border control register 1 (BB1) [Address 021D16] B Name 0 Control bits of to bottom border 7 (BB10 to BB17) After reset R W Functions Bottom border position (low-order 8 bits) Indeterminate R W TH (setting value of low-order 2 bits of BB2 162 + setting value of high-order 4 bits of BB1 161 + setting value of low-order 4 bits of BB1 160)
Notes 1: Set values fit for the following condition: (TB1 + TB2 162) < (BB1 + BB2 162). 2: TH is cycle of HSYNC. 3: BB2 is bottom border control reigster 2.
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
Address 021E16
Top Border Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0 Top border control register 2 (TB2) [Address 021E16] B Name 0, 1 Control bits of top border (TB20 ,TB21) After reset R W Functions Top border position (high-order 2 bits) Indeterminate R W TH (setting value of low-order 2 bits of TB2 162 + setting value of high-order 4 bits of TB1 161 + setting value of low-order 4 bits of TB1 160)
2 Nothing is assigned. These bits are write disable bits. Indeterminate R -- to When these bits are read out, the values are indeterminate. 7 Notes 1: Do not set "0016" or "0116" to the TB1 at TB2 = "0016." 2: TH is cycle of HSYNC. 3: TB1 is top border control register 1.
Address 021F16
Bottom Border Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0 Bottom border control register 2 (BB2) [Address 021F16] B Name 0, 1 Control bits of bottom border (BB20, BB21) After reset R W Functions Indeterminate R W Bottom border position (high-order 2 bits) TH (setting value of low-order 2 bits of BB2 162 + setting value of high-order 4 bits of BB1 161 + setting value of low-order 4 bits of BB1 160)
2 Nothing is assigned. These bits are write disable bits. Indeterminate R -- to 7 When these bits are read out, the values are indeterminate. Notes 1: Set values fit for the following condition: (TB1 + TB2 162) < (BB1 + BB2 162). 2: TH is cycle of HSYNC. 3: BB1 is bottom border control reigster 1.
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
Addresses 022016 to 022F16
Vertical Position Register 1i
b7 b6 b5 b4 b3 b2 b1 b0 Vertical position register 1i (VP1i) (i = 1 to 16) [Addresses 022016 to 022F16] B Name 0 Control bits of vertical to display start positions 7 (VP1i0 to VP1i7) (See note 1) After reset R W Functions Vertical display start positions Indeterminate R W (low-order 8 bits) TH (setting value of low-order 2 bits of VP2i 162 + setting value of low-order 4 bits of VP1i 161 + setting value of low-order 4 bits of VP1i 160)
Notes 1: Do not "0016" and "0116" to VP1i at VP2i = "0016." 2: TH is cycle of HSYNC. 3: VP2i is vertical position register 2i.
Addresses 023016 to 023F16
Vertical Position Register 2i
b7 b6 b5 b4 b3 b2 b1 b0 Vertical position register 2i (VP2i) (i = 1 to 16) [Addresses 023016 to 023F16] B Name 0, 1 Control bits of vertical display start positions (VP2i0, VP2i1) (See note 1) After reset R W Functions Vertical display start positions Indeterminate R W (high-order 2 bits) TH (setting value of low-order 2 bits of VP2i 162 + setting value of low-order 4 bits of VP1i 161 + setting value of low-order 4 bits of VP1i 160)
2 Nothing is assigned. These bits are write disable bits. Indeterminate R -- to When these bits are read out, the values are indeterminate. 7 Notes 1: Do not set "0016" and "0116" to VP1i at VP2i = "0016." 2: TH is cycle of HSYNC. 3: VP1i is vertical position register 1i.
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
Addresses 024116 to 024716, 024916 to 024F16
Color Pallet Register i
b7 b6 b5 b4 b3 b2 b1 b0 Color pallet register i (CRi) (i = 1 to 7, 9 to15) [Addresses 024116 to 024716, 024916 to 024F16]
B
Name
b0 b1
Functions 0 0 1 1 0 0 1 1 0 0 1 1 0: No output (See note) 1: 1/3 V CC 0: 2/3 V CC 1: V CC 0: No output (See note) 1: 1/3 V CC 0: 2/3 V CC 1: V CC 0: No output (See note) 1: 1/3 V CC 0: 2/3 V CC 1: V CC
Afterreset R W Indeterminate R W
0, 1 R signal output control bits (CRi0, CRi1)
2, 3 G signal output control bits (CRi2, CRi3)
b3 b2
Indeterminate R W
4, 5 B signal output control bits (CRi4, CRi5)
b5 b4
Indeterminate R W
6 7
OUT1 signal output control bit (CRi6)
0: No output 1: Output
Indeterminate R W Indeterminate R --
Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is indeterminate.
Note: When selecting digital output, the output is VCC at all values other than "00."
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
Address 025016
Left Border Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0 Left border control register 1 (LB1) [Address 025016]
B 0 1 to 7
Name Control bits of left border (LB10 to LB17)
Functions Left border position (low-order 8 bits) TOSC (setting value of low-order 3 bits of LB2 162 + setting value of high-order 4 bits of LB1 161 + setting value of low-order 4 bits of LB1 160)
After reset R W 1 0 RW
Notes 1: Do not set LB1 = LB2 = "0016." 2: Set values fit for the following condition: (LB1 + LB2 162) < (RB1 + RB2 162). 3: TOSC is OSD oscillation period. 4: LB2 is left border control register 2.
Address 025116
Left Border Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0 Left border control register 2 (LB2) [Address 025116]
B 0 to 2
Name Control bits of left border (LB20 to LB22)
Functions Left border position (high-order 3 bits) TOSC (setting value of low-order 3 bits of LB2 162 + setting value of high-order 4 bits of LB1 161 + setting value of low-order 4 bits of LB1 160)
After reset R W 0 RW
3 Nothing is assigned. These bits are write disable bits. to When these bits are read out, the values are indeterminate. 7 Notes 1: Do not set LB1 = LB2 = "0016." 2: Set values fit for the following condition: (LB1 + LB2 162) < (RB1 + RB2 162). 3: TOSC is OSD oscillation period. 4: LB1 is left border control register 1.
0
RW
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
Address 025216
Right Border Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0 Right border control register 1 (RB1) [Address 025216]
B 0 to 7
Name Control bits of right border (RB10 to RB17)
Functions Right border position (low-order 8 bits) TOSC (setting value of low-order 3 bits of RB2 162 + setting value of high-order 4 bits of RB1 161 + setting value of low-order 4 bits of RB1 160)
After reset R W 1 RW
Notes 1: Set values fit for the following condition: (LB1 + LB2 162) < (RB1 + RB2 162). 2: TOSC is OSD oscillation period. 3: RB2 is right border control register 2.
Address 025316
Right Border Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0 Right border control register 2 (RB2) [Address 025316]
B 0 to 2
Name Control bits of right border (RB20 to RB22)
Functions Right border position (high-order 3 bits) TOSC (setting value of low-order 3 bits of RB2 162 + setting value of high-order 4 bits of RB1 161 + setting value of low-order 4 bits of RB1 160)
After reset R W 1 RW
3 to 7
Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0".
0
RW
Notes 1: Set values fit for the following condition: (LB1 + LB2 162) < (RB1 + RB2 162). 2: TOSC is OSD oscillation period. 3: RB1 is right border control register 1.
Rev.1.00 Apr 01, 2002 REJ03B0130-0100Z
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
Address 025416
SPRITE Vertical Position Register 1
b7 b6 b5 b4 b3 b2 b1 b0 SPRITE vertical position register 1 (VS1) [Address 025416]
B 0 1 to 7
Name Vertical display start position control bits of SPRITE OSD (VS10 to VS17)
Functions Vertical display start position (low-order 8 bits) TH (setting value of low-order 2 bits of VS2 162 + setting value of high-order 4 bits of VS1 161 + setting value of low-order 4 bits of VS1 160)
After reset R W 1 0 RW
Notes 1: Do not set "0016" to the VS1 at VS2 = "0016." 2: TH is cycle of HSYNC. 3: VS2 is SPRITE vertical position register 2.
Address 025516
SPRITE Vertical Position Register 2
b7 b6 b5 b4 b3 b2 b1 b0 SPRITE vertical position register 2 (VS2) [Address 025516]
B
Name
Functions Vertical display start position (high-order 2 bits) TH (setting value of low-order 2 bits of VS2 162 + setting value of high-order 4 bits of VS1 161 + setting value of low-order 4 bits of VS1 160)
After reset R W 0 RW
0, 1 Vertical start position control bits of SPRITE OSD (VS20, VS21)
2 Nothing is assigned. These bits are write disable bits. to When these bits are read out, the values are "0". 7 Notes 1: Do not set "0016" to the VS1 at VS2 = "0016." 2: TH is cycle of HSYNC. 3: VS1 is SPRITE vertical position register 1.
0
R--
Rev.1.00 Apr 01, 2002 REJ03B0130-0100Z
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
Address 025616
SPRITE Horizontal Position Register 1
b7 b6 b5 b4 b3 b2 b1 b0 SPRITE horizontal position register 1 (HS1) [Address 025616] B Name 0 Horizontal display to start position control 7 bits of SPRITE OSD (HS10 toHS17) After reset R W Functions Horizontal display start position (low-order 8 bits) Indeterminate R W TOSC (setting value of low-order 2 bits of HS2 162 + setting value of high-order 4 bits of HS1 161 + setting value of low-order 4 bits of HS1 160)
Notes 1: Do not set HS1 < "3016" at HS2 = "0016." 2: TOSC is OSD oscillation period. 3: HS2 is SPRITE horizontal position register 2.
Address 025716
SPRITE Horizontal Position Register 2
b7 b6 b5 b4 b3 b2 b1 b0 SPRITE horizontal position register 2 (HS2) [Address 025716] B Name 0 Horizontal display to start position control 2 bits of SPRITE OSD (HS20 to HS22) After reset R W Functions Horizontal display start position (high-order 3 bits) Indeterminate R W TOSC (setting value of low-order 2 bits of HS2 162 + setting value of high-order 4 bits of HS1 161 + setting value of low-order 4 bits of HS1 160) 3 Nothing is assigned. These bits are write disable bits. 0 R-- to When these bits are read out, the values are "0." 7
Notes 1: Do not set HS1< "3016" at HS2 = "0016." 2: TOSC is oscillation period. 3: HS1 is SPRITE horizontal position register 1.
Rev.1.00 Apr 01, 2002 REJ03B0130-0100Z
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
Address 025816
SPRITE OSD Control Register
b7 b6 b5 b4 b3 b2 b1 b0 SPRITE OSD control register (SC) [Address 025816]
B 0
Name SPRITE OSD control bit (SC0) Pre-divide ratio selection bit (SC1) 0: Stopped 1: Operating
Functions
After reset R W 0 RW
1
0: Pre-divide ratio 1 1: Pre-divide ratio 2 b3 0 0 1 1 b2 0: 1Tc 1/2H 1: 1Tc 1H 0: 2Tc 1H 1: 2Tc 2H
0
RW
2, 3 Dot size selection bits (SC2, SC3)
0
RW
4
Interrupt occurrence position selection bit (SC4) XIN/4096 * SPRITE interrupt source switch bit (SC5)
0: After display of horizontal 20 dots 1: After display of horizontal 10 dots or 20 dots 0: XIN/4096 interrupt 1: SPRITE OSD interrupt
0
RW
5
0
RW
6, 7
Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0".
0
R--
Notes 1: Tc : Pre-devided clock period for OSD 2: H : HSYNC
Rev.1.00 Apr 01, 2002 REJ03B0130-0100Z
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M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
19. PACKAGE OUTLINE
64P4B
EIAJ Package Code SDIP64-P-750-1.78 JEDEC Code - Weight(g) 7.9 Lead Material Alloy 42
Plastic 64pin 750mil SDIP
64
33
1
32
Symbol
D
e SEATING PLANE
b1
b
b2
A A1 A2 b b1 b2 c D E e e1 L
Dimension in Millimeters Max Nom Min 5.08 - - - - 0.38 - 3.8 - 0.6 0.5 0.4 1.3 1.0 0.9 1.05 0.75 0.65 0.32 0.25 0.2 56.6 56.4 56.2 17.15 17.0 16.85 - 1.778 - - 19.05 - - - 2.8 15 - 0
L
A
Rev.1.00 Apr 01, 2002 REJ03B0130-0100Z
page 169 of 169
A1
A2
e1
E
c
REVISION HISTORY
Rev. Date Page 1.00 Apr 01, 2002 -
M37280MFH-XXXSP, M37280MKH-XXXSP, M37280EKSP
Description Summary
First edition issued
A-1
Sales Strategic Planning Div.
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